Fabrication method of a BIMOS semiconductor device

Fishing – trapping – and vermin destroying

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437 59, 437162, 437228, 437231, 148DIG9, H01L 21331, H01L 21336

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050454846

ABSTRACT:
A method for fabricating a BIMOS device includes steps of forming a first insulator layer on the semiconductor layer in correspondence to a first region, providing a gate electrode of a metal-insulator-semiconductor transistor on the first insulator layer, and providing a base electrode of a bipolar transistor on a second region of the semiconductor layer. The method also includes introducing impurities into the semiconductor layer in the first region using the gate electrode as a mask to form self-aligned source and drain regions, introducing impurities into the base electrode and causing a diffusion of the impurities into the semiconductor layer to form a base region in the second region. Also included are steps of providing a second insulator layer so as to cover the first region and the second region, providing an insulator material on the second insulator in the form of liquid and curing subsequently to form a third insulator layer on the second insulator layer with a planarized top surface. A through hole is provided in the second insulator layer such that the through hole penetrates at least through the second insulator layer and the base electrode to expose a top surface of the semiconductor layer. An emitter region of the bipolar transistor is formed in the second region of the semiconductor layer. Interconnection electrodes for interconnection of the semiconductor device are also provided.

REFERENCES:
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patent: 4753709 (1988-06-01), Welch et al.
patent: 4829025 (1989-05-01), Iranmanesh
patent: 4902640 (1990-02-01), Sachitano et al.
patent: 4931407 (1990-06-01), Maeda et al.
Chiu, T. Y., et al., IEEE Electron Device Letters, vol. 11, No. 2, Feb. 1990, pp. 85-86.
Takemura, H., et al., IEEE IEDM Technical Digest, 1987, pp. 375-378.
Gomi, T., et al., IEEE IEDM Technical Digest 1988, pp. 744-747.

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