Fabrication method for shallow trench isolation region

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S427000, C438S433000, C438S434000, C438S435000, C438S437000, C438S766000

Reexamination Certificate

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06911374

ABSTRACT:
A fabrication method for a shallow trench isolation region is described. A part of the trench is filled with a first insulation layer, followed by performing a surface treatment process to form a surface treated layer on the surface of a part of the first insulation layer. The surface treated layer is then removed, followed by forming a second insulation layer on the first insulation layer and filling the trench to form a shallow trench isolation region. Since a part of the trench is first filled with the first insulation layer, followed by removing a portion of the first insulation layer, the aspect ratio of the trench is lower before the filling of the second insulation in the trench. The adverse result, such as, void formation in the shallow trench isolation region due to a high aspect ratio, is thus prevented.

REFERENCES:
patent: 5401998 (1995-03-01), Chiu et al.
patent: 2002/0100952 (2002-08-01), Hong
patent: 2003/0143789 (2003-07-01), Su et al.

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