Fabrication method for semiconductor integrated circuits

Details Fabrication method for semiconductor integrated circuits Fabrication method for semiconductor integrated circuits

1988-09-16

1989-09-12

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437162, 437909, 357 34, 357 59, H01L 2972

Patent

active

048660000

ABSTRACT:
In method of fabricating a bipolar transistor on a semiconductor substrate, the emitter pattern is formed using the horizontal etching effect and filling-in effect of the RF-bias sputtering method, so a fine, self-aligned emitter pattern can be created that is disposed entirely in the center of the active base region without the use of photoetching. In addition, the passive base layer and the emitter layer can approach each other to any desired degree as long as they do not touch, so no high-concentration base layer is necessary, the base resistance is reduced, and the passive base region is reduced to a very small size. Furthermore, after the formation of the base region, the only heat treatment step that alters the diffusion layer profile is the formation of the emitter layer, so the use of a thin epitaxial layer to reduce the collector resistance does not result in proximity of the buried collector layer and the passive base layer.

REFERENCES:
patent: 4492008 (1985-01-01), Anantha et al.
patent: 4693782 (1987-09-01), Kikuchi et al.
patent: 4735912 (1988-04-01), Kawakatsu
patent: 4749663 (1988-06-01), Okita

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