Fabrication method for semiconductor device, exposure...

Details Fabrication method for semiconductor device, exposure... Fabrication method for semiconductor device, exposure...

2011-04-05

2011-04-05

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

C716S051000, C716S052000, C716S054000

Reexamination Certificate

active

07921386

ABSTRACT:
Disclosed herein is a fabrication method for a semiconductor device, including a lithography step of connecting a plurality of mask patterns to each other to form a pattern image of an area greater than the size of the mask patterns. The lithography step includes the steps of: assuring an overlapping exposure region to be exposed in an overlapping relationship by both of two mask patterns to be connected to each other, carrying out exposure transfer of the pattern portions of the two mask patterns to the overlapping exposure region to form a first measurement mark and a second measurement mark in the overlapping exposure region, and carrying out positional displacement measurement of pattern connection by the two mask patterns based on a manner of combination of main marks and sub marks of the measurement marks formed in the overlapping exposure region.

REFERENCES:
patent: 7003757 (2006-02-01), Pierrat et al.
patent: 09-293661 (1997-11-01), None
patent: 2001-015419 (2001-01-01), None
patent: 2001-093818 (2001-06-01), None
patent: 2004-200509 (2004-01-01), None
patent: 2007-067018 (2007-03-01), None
Office Action issued by the Japanese Patent Office on May 12, 2009 in connection to related Japanese Patent Application No. 2007-117847.

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