Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-05-08
2004-09-28
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S725000, C430S297000
Reexamination Certificate
active
06797635
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 91106125, filed Mar. 28, 2002.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for lines of a semiconductor device.
2. Background of the Invention
With the demand for higher levels of integration of semiconductor devices, the need for reduced device dimensions and patterns having a finer linewidth greatly increases. The photolithography technique in the semiconductor processing plays a significant role in influencing the density of semiconductor devices because processes including etching and doping are accomplished through photolithography. Thus, whether the integration of the semiconductor industry can be developed beyond a linewidth of 0.15 &mgr;m is determined by the advancement of the photolithography technique. In order to accommodate this demand, methods, for example, optical proximity correction (OPC) are being proposed to enhance the resolution of the photomask.
In general, in the manufacturing of the 0.18 &mgr;m linewidth and beyond, the light deflection problem becomes more serious as the dimensions of the holes and the lines are being reduced. Optical proximity correction is thus used to eliminate the deviation in the critical dimension (CD) resulted from the proximity effect. The proximity effect is due to, on one hand, the scattering of a light beam causing the light to enlarge when the light beam is incident on a wafer through the pattern of a mask. While on the other hand, the light beam is reflected from the semiconductor substrate of the wafer through the photoresist layer on the surface of the wafer, causing an interference with the incident light beam. The actual intensity of the exposure light on the photoresist layer is thus altered due to multiple exposures. This type of effect is especially obvious, as the critical dimension of a process becomes smaller; especially the critical dimension approaches the wavelength of the incident light.
OPC is conventionally used to improve the mask resolution such that the dimension of the photoresist subsequent to exposure is same as the expected dimension. However, the dimension of the pattern resulted from the etching process is usually different and deviated from the expected device dimension. Such deviation is due to the microloading effect resulted from the etching process subsequent to the photolithography process. The microloading effect is generally referred to the undue changes in the etching rate, shape or etching attribute. These undue changes are typically resulted from a higher etching rate in the ISO region than in the DENSE region, leading to deviation in the critical dimension and eventually in the dimension of the entire semiconductor device.
Conventionally, to resolve the microloading effect in an etching process the etching recipe is altered, for example, altering the etching gas, the power of the etching process, etc. However, to simply altering the etching method has a limited effect on mitigating the microloading effect. Moreover, the manufacturing processing becomes more complex.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a fabrication method for lines of a semiconductor device, wherein same linewidths are formed in regions of different densities.
The present invention also provides a fabrication method for lines of a semiconductor device, wherein problems of deviation in the device dimension are prevented.
The present invention further provides a fabrication method for lines of a semiconductor device, wherein the fabrication of lines of a semiconductor device can be simplified.
In accordance to the above and other objectives, the present invention provides a fabrication method for lines of a semiconductor device which comprises providing a deposition layer, followed by forming a photoresist layer on the deposition layer. A photolithography process is then conducted to pattern the photoresist layer using a mask, wherein the proximity effect and the microloading effect due to the etching process are taken into consideration in the design of the mask. Thereafter, using the patterned photoresist layer as an etching mask, the deposition layer is etched to form a plurality of lines, wherein these lines are formed in both the dense feature region and the scattered and isolated region. Thereafter, the patterned photoresist is removed.
The present invention provides a fabrication method for a pattern of a semiconductor device, which includes providing a substrate that comprises a deposition layer. A patterned photoresist layer is then formed on the deposition layer, wherein the patterned photoresist layer comprises a plurality of first patterns and second patterns for forming a plurality of lines, wherein a width of the first patterns is greater than a linewidth of the lines, a bottom width of the second patterns is same as the linewidth of the lines and a top width of the second patterns is smaller than the top width of the second patterns. Using the patterned photoresist layer as an etching mask, an etching is conducted on the deposition layer to form the plurality of lines. After this, the pattern photoresist layer is removed.
Since during the patterning of the photoresist layer, the proximity effect and the microloading effect resulted from the etching process are being considered, the difference in the linewidths between the dense feature region and the scattered and isolated feature region is minimized. Even in regions with different pattern density, the dimension of the resulted pattern is close to the expected pattern dimension.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5308740 (1994-05-01), Templeton et al.
patent: 6069090 (2000-05-01), Eriguchi
J. C. Patents
Vinh Lan
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