Fabrication method for integrated circuits with polysilicon line

Details Fabrication method for integrated circuits with polysilicon line Fabrication method for integrated circuits with polysilicon line

1977-11-11

1978-12-05

Weiffenbach, Cameron K.

Coating processes

Electrical product produced

Condenser or capacitor

427 88, 427 93, 427 96, 427272, 357 67, B05D 512

Patent

active

041286707

ABSTRACT:
A method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance. The invention may be employed in a polysilicon gate MOSFET process for integrated circuits as well as other integrated structures. In the method a first layer of polysilicon is deposited followed by a deposition of a metal of the silicide forming type. Another polysilicon layer is then deposited on top of the silicide forming metal to produce a three layer structure. The three layer structure is subjected to heat, for example, during the reoxidation step in a gate fabrication process, the metal reacts with the polysilicon at two reaction fronts to form a silicide. The resultant silicide has a much lower resistivity than doped polysilicon and therefore provides a second conductive layer which can be used more compatibly and efficiently in connection with the normal metal layer employed in integrated circuits to give a two-dimensional degree of freedom for the distribution of signals.

REFERENCES:
patent: 3375418 (1968-03-01), Garnache et al.
patent: 3987216 (1976-10-01), Bhatia et al.
Rideout; V. L., Reducing the Sheet Resistance of Polysilicon Lines in Integrated Circuits, In IBM Technical Disclosure Bull., vol. 17, No. 6, Nov. 1974, pp. 1831-1833.

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