Fabrication method for high conductivity, void-free polysilicon-

Metal treatment – Compositions – Heat treating

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29571, 156653, 156657, 427 89, 427 93, H01L 21285

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active

043892574

ABSTRACT:
A method of providing self-passivating interconnection electrodes for semiconductor devices which provides low resistivity composite polysiliconsilicide electrodes. In the method the formation of oxidation induced voids in polysilicon underlying the silicide is eliminated by deposition of polysilicon and stoichiometric proportions of silicon and a silicide-forming metal. These steps are followed by deposition of a silicon layer having a thickness determined to provide between 30 and 100 percent of the silicon required to form a silicon dioxide passivation layer. Subsequent thermal oxidation of the layered electrode structure provides a self-passivated structure useful for fabrication of silicon gate MOSFET devices as well as other integrated circuit structures.

REFERENCES:
patent: 3381182 (1968-04-01), Thornton
patent: 3881971 (1975-05-01), Greer et al.
patent: 3911168 (1975-10-01), Schinella
patent: 4128670 (1978-12-01), Gaensslen
patent: 4152823 (1979-05-01), Hall
patent: 4180596 (1979-12-01), Crowder et al.
patent: 4228212 (1980-10-01), Brown et al.
patent: 4332839 (1982-06-01), Levinstein
Rideout, V. L., "Reducing the Sheet Resistance of Polysilicon Lines in Integrated Circuits", IBM Tech. Disc. Bul., vol. 17, No. 6, pp. 1831-1833 (11-74).
Baglin, J. E. et al., "Fabrication of Conductive Refractory Silicide-Doped Polysilicon Lines", IBM Tech. Discl. Bul., vol. 20, No. 10, p. 4189 (3-78).
Howard, J. K. "Gate for MOS Devices: Rare Earth Silicides", IBM Tech. Discl. Bul., vol. 21, No. 7, pp. 2811-2813 (12-78).
Zirinsky, S. et al., "Oxidation Mechanisms in WSi.sub.2 Thin Films", Appl. Phys. Lett., vol. 33, No. 1, 1 Jul. 1978, pp. 76-78.
Crowder, B. L., et al., ". . . Metal Silicide Interconnection Technology--A Future Perspective", IEEE J. Sol-St. Cir., vol. SC-14, No. 2, pp. 291-293 (4-79).
Murarka, S. P., "Refractory Silicides for Low Resistivity Gates and Interconnects", IEDM 1979, Tech. Dig. Paper 20.1, pp. 454-457 (12-03-79).
Hsieh, N. et al., "Oxidation Induced Voids in Polysilicon/Silicide Films", Spring Meeting, Electrochem. Soc., vol. 80-1, Abs. 161, pp. 425-427 (5-11-80).
Koburger, C. et al., "Electrical Properties of Composite Silicide Gate Electrodes", Spring Meeting, Electrochem. Sol., vol. 80-1, Abs. 162, pp. 428-430 (5-11-80).

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