Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Patent
1997-09-25
1999-01-26
Niebling, John F.
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
438466, 205123, 205128, H01L 21326, H01L 21479
Patent
active
058638164
ABSTRACT:
A fabrication method for a chip size semiconductor package includes the steps of bonding conductive wires on bonding pads formed on an upper surface of a semiconductor chip, putting the semiconductor chip including the bonded conductive wires in an electrolyzer containing an electrolytic solution in such a manner that one end of each of the conductive wires is exposed outside of the electrolytic solution, attaching a plating electrode to an inner wall of the electrolyzer, attaching a conductive plate to serve as a common electrode to the exposed one end of each of the conductive wires; and connecting the conductive plate and the outer wall of the electrolyzer to an electric current source.
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Lowenheim, Frederick A., Electroplating, McGraw-Hill, New York, pp. 152-155, 1978.
Jones Jositta
LG Semicon Co. Ltd.
Niebling John F.
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