Fabrication method for chip size package and non-chip size...

Details Fabrication method for chip size package and non-chip size... Fabrication method for chip size package and non-chip size...

2006-03-07

2009-12-15

Pham, Thanh V (Department: 2894)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S113000, C257S786000, C257SE21001

Reexamination Certificate

active

07632711

ABSTRACT:
When an integrated circuit is formed in a semiconductor wafer, the integrated circuit is formed only in the central part of each chip region. In a case where packaging other than a chip size package is made, only the central part in which the integrated circuit is formed is cut from the wafer. In a case where a chip size package is made, the chip region is cut from the wafer after forming the redistribution wiring and external terminals and so forth over the whole of the chip region. As a result, the design of the integrated circuit and part of the fabrication process thereof can be shared by a chip which is mounted in a chip size package and a chip which is mounted in another type of package.

REFERENCES:
patent: 5557148 (1996-09-01), Cain
patent: 6228684 (2001-05-01), Maruyama
patent: 6391685 (2002-05-01), Hikita et al.
patent: 6504096 (2003-01-01), Okubora
patent: 2001/0042901 (2001-11-01), Maruyama
patent: 2002/0074146 (2002-06-01), Okubora
patent: 2002/0149086 (2002-10-01), Aoki
patent: 2003/0189251 (2003-10-01), Terui et al.
patent: 9-64049 (1997-03-01), None
patent: 2000-243900 (2000-09-01), None
patent: 2000-299406 (2000-10-01), None

Affiliated with

Also associated with

Rating

Fabrication method for chip size package and non-chip size... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication method for chip size package and non-chip size..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication method for chip size package and non-chip size... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4069292