Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
2000-08-16
2001-10-02
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
C438S250000
Reexamination Certificate
active
06297121
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to methods of fabrication of capacitors in integrated circuits and more particularly for capacitors used in dynamic random access memory circuits.
(2) Description of the Related Art
Capacitors having sufficient capacitance are critical elements in dynamic random access memory, DRAM, circuits. As the size of the DRAM circuits decreases it becomes more difficult to fabricate DRAM capacitors having sufficient capacitance within the space allotted to each DRAM cell.
U.S. Pat. No. 6,049,101 to Graettinger et al. describes methods of forming a DRAM capacitor. A capacitor opening is formed over a substrate node location. Electrically conductive material is formed within the capacitor opening and makes electrical connection with the node location. A structure of conducting material and insulator material is used to form the capacitor.
SUMMARY OF THE INVENTION
It is a primary objective of this invention to provide methods of forming capacitor structures having increased capacitance within an integrated circuit area.
This objective is achieved by forming a first layer of silicon dioxide over an integrated circuit wafer having devices formed therein and a node location. A contact hole is formed in the layer of first layer of silicon dioxide thereby exposing a part of the node location. The contact hole is larger at the top of the contact hole than at the bottom of the contact hole. A self aligned contact is formed in the substrate through the contact hole.
A layer of polysilicon is then formed on the sidewalls and bottom of the contact hole. Silicon dioxide spacers are then formed on the polysilicon formed on the sidewalls of the contact hole so that a center cavity remains in the contact hole. The center cavity is then filled with polysilicon to form a center pillar which makes electrical contact with the polysilicon at the bottom of the contact hole. The silicon dioxide spacers are then etched away using hydrogen fluoride vapor leaving a polysilicon pillar in the contact hole and polysilicon on the sidewalls and bottom of the contact hole. The polysilicon pillar in the contact hole and the polysilicon on the sidewalls and bottom of the contact hole form the first plate of the capacitor.
A second layer of silicon dioxide is then deposited on the substrate thereby covering the polysilicon pillar in the contact hole and the polysilicon on the sidewalls and bottom of the contact hole. A side cavity remains surrounding the polysilicon pillar. A layer of polysilicon is then formed on the second layer of silicon dioxide to form the second capacitor plate. The polysilicon forming the second capacitor plate fills the side cavity.
In one embodiment a layer of hemispherical grain, HSG, polysilicon is formed on the polysilicon forming the first capacitor plate before the second layer of silicon dioxide is deposited. The HSG polysilicon will increase the capacitance of the capacitor.
REFERENCES:
patent: 5126280 (1992-06-01), Chan et al.
patent: 5364809 (1994-11-01), Kwon et al.
patent: 5438011 (1995-08-01), Blalock et al.
patent: 5821139 (1998-10-01), Tseng
patent: 5989953 (1999-11-01), Liang et al.
patent: 6049101 (2000-04-01), Graettinger et al.
Ackerman Stephen B.
Nelms David
Nhu David
Prescott Larry J.
Saile George O.
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