Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
1999-08-16
2001-03-06
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
75
Reexamination Certificate
active
06197700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a bottom electrode of a capacitor. More particularly, the present invention relates to a fabrication method for a landing pad of a capacitor.
2. Description of the Related Art
As the density of integrated circuits increases, the formation of a contact node in the manufacturing of a capacitor usually employs a self-aligned contact window approach. Since the aspect ratio of the desired opening formed in the self-aligned contact window process is often too high, the quality of the etching is reduced and the etching conditions become more difficult to control.
FIGS. 1A and 1B
are schematic, cross-sectional views of a self-aligned contact window showing the steps for manufacturing a self-aligned contact window according to the conventional methods.
Referring to
FIG. 1A
, a substrate
100
comprising an isolation layer
102
, an etching stop layer
104
and a landing pad
106
is provided. A dielectric layer
108
is then formed covering the entire substrate
100
, followed by forming bit line structures
110
and spacers
112
on the dielectric layer
108
. The bit line structures
110
comprise a polysilicon layer
114
, an adhesive layer
116
and a protective layer
118
. Since the protective layer
118
, for example, is a nitride layer and the dielectric layer
108
, for example, is an oxide layer, the protective layer and the dielectric layer thereby exhibit a higher etching ratio. The adhesive layer
116
, for example, tungsten or a tungsten silicide material, is used to enhance the adhesion between the polysilicon layer
114
and the protective layer
118
.
As shown in
FIG. 1B
, an oxide layer
120
is formed, covering the entire substrate
100
. Anisotropic etching is conducted, by means of a photolithography and etching technique, to remove the dielectric layer
108
and the oxide layer
120
above the landing pad
106
. A contact window opening
122
is thus formed, exposing the landing pad
106
. Since the position in forming the node contact window opening
122
is not completely aligned with the landing pad, the bit line structure
110
is etched. Since the bit line structure
110
includes the protective layer
118
, the bit line structure
110
is protected from further etching by the protective layer
118
.
The aspect ratio of the node contact window opening
122
formed by the above approach is, however, too high. The dielectric layer
108
and the oxide layer
120
in the node contact window opening
122
are thereby not completely removed (not shown in Figure), resulting in an incomplete exposure of the landing pad
106
. Furthermore, although the protective layer
118
has a different etching ratio from the oxide material, it is more difficult to control the etching condition because the node contact window opening formed by this approach is too deep. If the etching condition is inappropriate or the etching period is too long, the protective layer is etched away and the adhesive layer
116
of the bit line structure
110
is exposed while forming the node contact window opening
122
.
SUMMARY OF THE INVENTION
The current invention provides a fabrication method for a bottom electrode of a capacitor, in which a dielectric layer is formed on a substrate already comprising an isolation layer, an etching stop layer and a landing pad. Bit line structures and spacers are further formed on the dielectric layer. The bit line structures comprise a polysilicon layer, an adhesive layer, a protective layer and an oxide layer. The spacers are located on the sidewalls of the bit line structures. The oxide layer of the bit line structures and a portion of the dielectric layer are further removed to form a node contact window opening in the dielectric layer exposing the landing pad. A conformal first conductive layer is formed on the substrate, and a patterned mask layer is formed on the first conductive layer. The mask layer only covers the first conductive layer between the bit line structures, and a portion of the first conductive layer is thereby exposed. An etching-back technique is used to remove the exposed first conductive layer, followed by forming a conformal second conductive layer to cover the entire substrate. Another etching-back procedure is performed to remove a portion of the second conductive layer to form an extended portion connecting to the first conductive layer, and to remove the mask layer.
One of the salient features of the present invention is that the formation of a bottom electrode for a capacitor is conducted in two separate steps. First, a first conductive layer is formed connecting to the landing pad in the node contact window opening, after which a patterned mask layer and a conformal second conductive layer on the substrate are formed, followed by an etching-back procedure on the second conductive layer to form the extended portion which is connected to the landing pad. The first conductive layer and the extended portion together form the bottom electrode for the capacitor. Since only the dielectric layer above the landing pad is removed when forming the node contact window opening, the dielectric layer above the landing pad is guaranteed to be completely removed during the etching process. Furthermore, the node contact window opening formed according to the present invention is shallow. Even if the position of the node contact window opening is not completely aligned with the landing pad, only a limited portion of the protective layer in the bit line structure is etched away. The etching conditions thus have a greater tolerance for error and the etching process is therefore easier to control.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5380673 (1995-01-01), Yang et al.
patent: 5650349 (1997-07-01), Prall et al.
patent: 5731130 (1998-03-01), Tseng
Chiou Jung-Chao
Wang Chuan-Fu
Oppenheimer Wolff & Donnelly LLP
Umez-Eronini Lynette T.
United Microelectronics Corp.
Utech Benjamin L.
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