Fabrication method for BiMOS semiconductor devices with improved

Details Fabrication method for BiMOS semiconductor devices with improved Fabrication method for BiMOS semiconductor devices with improved

1990-12-27

1992-03-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 56, 437 31, 437913, 148DIG9, H01L 21265

Patent

active

051008157

ABSTRACT:
To create bipolar and MOS transistors, a substrate is covered with polysilicon. The polysilicon is patterned to form gate electrodes in MOS transistor regions, and to form polysilicon patterns surrounding central openings in bipolar transistor base-and-emitter regions. Lightly-doped source and drain layers are created by implanting impurities into the MOS transistor regions, using the gate electrodes as masks. Active bases are formed in the base-and-emitter regions below the central openings. Then sidewalls are added to the polysilicon, narrowing the central openings and widening the gate electrodes. Impurities are implanted into the MOS transistor regions, using the widened gate electrodes as masks, to create heavily-doped source and drain layers. The active base areas are doped below the narrowed central openings to create emitters.

REFERENCES:
patent: 4727038 (1988-02-01), Watabe et al.
patent: 4731341 (1988-03-01), Kawakatsu
patent: 4873200 (1989-10-01), Kawakatsu
patent: 4891328 (1990-01-01), Gris
patent: 4957874 (1990-09-01), Soejima
patent: 4975381 (1990-12-01), Taka et al.
"High Performance LSI Process Technology: SST CBi-CMOS," Kobayashi et al., Extended Abstracts of IEDM '88, pp. 760-763.

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