Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-03-06
2002-06-18
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
Reexamination Certificate
active
06406971
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a memory device. More particularly, the present invention relates to a fabrication method for an embedded direct random access memory (DRAM).
2. Description of the Related Art
Embedded dynamic random access memory (DRAM) are integrated devices that integrate a memory cell array and logic circuit array on a single wafer. Embedded DRAM can store large amounts of information at very high speeds and are of great benefit to the use of the integrated circuit. Often Embedded DRAM is applied to a logic circuit that processes large amounts of data, such as a graphic processor. A complete embedded DRAM comprises a logic circuit, a transfer field effect transistor (FET), and a capacitor coupled to a transfer field effect transistor. The transfer FET controls the connection between the capacitor's bottom electrode and the bit line. Thus, information can either be read from the capacitor or stored in the capacitor.
FIGS. 1A-1F
are schematic drawings illustrating the conventional method of fabricating an embedded DRAM. As shown in
FIG. 1A
, a substrate is provided. A (metal oxide semiconductor) MOS transistor
110
is then formed above the P-type MOS region
106
and N-type MOS region
108
of the memory cell region
102
and the periphery circuit region
104
of the substrate
100
. Afterwards, a barrier layer
111
is formed over the substrate
100
in order to cover a predetermined area where a self-aligned silicide is not formed. After conducting a self-aligned silicide fabrication process, a dielectric layer
112
is formed over the substrate
100
. A landing pad
114
is then formed in the dielectric layer
112
of the memory cell region
102
of the substrate
100
(as shown in FIG.
1
B).
Referring to
FIG. 1C
, a dielectric layer
116
is formed over the substrate
100
, while a photoresist layer
123
is formed on the dielectric layer
116
. With the photoresist serving as a mask, an etching step is performed to form a contact opening
118
in the dielectric layer
116
from the memory cell region
102
. Simultaneously, contact openings
120
,
122
are formed in the dielectric layers
112
,
116
from the PMOS region
106
and NMOS region
108
of the peripheral circuit region
104
, respectively.
Referring to
FIGS. 1D and 1E
, the photoresist
123
is removed. Conventionally, N-type ions and P-type ions would then be implanted into the NMOS region
106
and PMOS region
108
of the peripheral circuit region
104
before the contact openings
120
,
122
are filled with a tungsten layer for forming contact windows, in order to reduce the current leakage from subsequently formed salicide region (source/drain region) on the substrate
100
. However, the contact openings
120
,
122
are formed simultaneously in the photolithographic and etching process for forming the bit line contact opening
118
. So, when the MOS devices exposed in the contact openings
122
,
120
are implanted with N-type ions and P-type ions respectively, extra photoresist would be required to cover contact openings
120
,
118
or contact openings
122
,
118
to make sure ions are implanted only into the contact opening
120
or
122
. As shown in
FIG. 1D
, that means forming a photoresist
124
on the dielectric layer
116
for covering the contact openings
118
,
120
before performing a N-type ion implantation on the MOS device exposed in the contact opening
122
. As shown in
FIG. 1E
, the photoresist
124
is removed. After that, a photoresist
128
is formed on the dielectric layer
116
for covering the contact openings
118
,
122
before a P-type ion implantation is performed on the MOS device exposed in the contact opening
120
. Next, referring to
FIG. 1F
, the contact openings
118
,
120
,
122
are filled with a tungsten layer, so that a contact window
132
connecting to the memory cell region
102
is formed together with contact windows
134
,
136
connecting respectively to the PMOS region
106
and NMOS region
108
. Then, a bit line
138
is formed over the memory cell region
102
of the substrate
100
, while forming a first metal layer
140
,
142
over the peripheral circuit region
104
, before any subsequent steps for fabricating the capacitor are performed.
In order to reduce the current leakage in the region where a self aligned silicide is not formed (i.e. the source/drain region), P-type and N-type ion implantation processes are typically conducted in the MOS device exposed by contact openings
120
and
122
, before the contact openings are filled with a tungsten layer. However, contact openings
120
and
122
are formed by the same photoligthographic etching process in which the bit-line contact
118
is formed. Thus, an additional photoresist layer must be formed over the MOS exposed by the contact opening
122
, during the implantation of N-type ions or over the MOS exposed by the contact opening
120
during the implantation of P-type ions. The photoresist layers
124
and
128
are formed to make sure that the ions are only implanted into the contact opening
122
or the contact opening
120
. Accordingly, the conventional fabrication process requires the additional cost of two masks and increases, as a consequence, the number of fabrication steps, which also affects yield.
SUMMARY OF THE INVENTION
The invention provides a fabrication method for an embedded dynamic random access memory. In this method, after several landing pads are formed on the substrate, a dielectric layer is formed over the substrate. A bit-line contact opening that exposes the landing pad, and a contact opening that exposes the N-type MOS in the periphery circuit region is formed in the dielectric layer. An N-type ion implantation step is performed to implant N-type ions into the landing pad and N-type MOS. Afterwards, the first bit-line contact opening and the first contact opening are filled with a conductive layer to form a bit-line contact and first contact. A bit-line electrically connected to the bit-line contact is formed. Another dielectric layer is formed over the substrate. In the aforementioned dielectric layer, a storage node contact opening that exposes another landing pad and a second contact opening that exposes a P-type MOS in the periphery circuit region are formed. A P-type ion implantation is performed to implant P-type ions into the landing pad and the P-type MOS exposed by the second contact opening. The storage node contact opening and the second contact opening are filled with a conductive layer, to form a storage node contact and a second contact. A capacitor that is electrically connected to the storage node contact is then formed.
In the method of the present invention a bit-line contact opening is formed as the contact opening exposing the N-type MOS in the periphery circuit region is formed. However, a contact opening that exposes the P-type MOS in the periphery circuit region is not formed. Rather, a second contact opening that exposes the P-type MOS in the periphery circuit region is formed as the storage node contact is formed. Thus, following the formation of the bit-line contact and the storage node contact, an N-type and P-type ion implantation can be performed, to implant both N-type or P-type ions into the substrate without having to form an additional photoresist layer. As a result, the reduction of current leakage in the area where a self-aligned silicide is not formed can be attained through the implantation process.
Accordingly, through the present invention the number of photoresists used can be reduced. Moreover, the number of fabrication steps as well as fabrication cost can be reduced, resulting in an increased of the yield. Additionally, present invention provides an embedded dynamic random access memory (DRAM) that reduces current leakage in the area where a self-aligned silicide is not formed
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended t
Chien Sun-Chieh
Kuo Chien-Li
Le Thao Phuong
Nelms David
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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