Fabrication method for a semiconductor structure

Details Fabrication method for a semiconductor structure Fabrication method for a semiconductor structure

2007-09-04

2007-09-04

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S710000, C257SE21597

Reexamination Certificate

active

11099962

ABSTRACT:
The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

REFERENCES:
patent: 6159862 (2000-12-01), Yamada et al.
patent: 6277706 (2001-08-01), Ishikawa
patent: 2002/0039843 (2002-04-01), Ikeda et al.
patent: 2005/0156274 (2005-07-01), Yeo et al.
patent: 102 25 941 (2004-08-01), None
patent: 1041 613 (2000-10-01), None
patent: 2003234328 (2003-08-01), None
German Office Action dated Jan. 12, 2005.

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