Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-09-15
2002-09-24
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C216S041000, C216S079000, C438S723000, C438S743000
Reexamination Certificate
active
06455438
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for a semiconductor device, and in particular to a technique for forming an opening in a resist film and then annealing the resist film to make the diameter of the formed opening smaller.
2. Description of the Related Art
Conventionally, an opening such as a contact hole is formed in an insulation film or the like formed on a semiconductor substrate in the following manner.
First, the insulation film such as a silicon oxide film is formed on the entire surface of the semiconductor substrate. Next, a resist film is formed on the insulation film and is then exposed and developed, so as to form the opening in the resist film. The resist film having the opening thus formed is then subjected to an annealing process, thus making the diameter of the opening smaller. After making the diameter of the opening smaller, the insulation film is etched using the resist film as a mask.
According to the conventional method, however, since the diameter of the opening formed in the resist film is made smaller by annealing the resist film as described above, the amount of reduction in the diameter varies depending on the position of the opening. This makes it hard to form openings having a uniform shape for a film that is to be etched.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a fabrication method for a semiconductor device that can allow openings having a uniform shape to be formed in the film to be etched, even if the sizes of the openings formed in the resist film are reduced by the annealing process.
In order to achieve the above object, according to the present invention, openings having different shapes are formed in the resist film. More specifically, according to an aspect of the present invention, a fabrication method for a semiconductor method includes: forming a film to be etched on a semiconductor substrate; forming a resist film on the film to be etched; exposing the resist film to form a first pattern group and a second pattern group therein, the first pattern group including a plurality of first patterns having a first size, the second pattern group arranged outside of the first pattern group, including a plurality of second patterns larger than the first patterns; developing the resist film to form in the resist film, openings corresponding to the first patterns and the second patterns; and annealing the resist film to make the openings smaller.
In an embodiment of the present invention, the first pattern group is formed by exposure using a first mask, while the second pattern group is formed by exposure using a second mask different from the first mask.
In another embodiment of the present invention, in the first pattern group the first patterns are arranged at a substantially constant interval.
In still another embodiment of the present invention, the amount of exposure for forming the second pattern group is larger than that for forming the first pattern group.
In still another embodiment of the present invention, an opening of the first mask has a smaller diameter than that of an opening of the second mask.
In still another embodiment of the present invention, the diameter of each of the openings corresponding to the first patterns after the annealing is substantially the same as the diameter of each of the openings corresponding to the second patterns after the annealing.
According to another aspect of the present invention, a fabrication method for a semiconductor device includes: forming a film to be etched on a semiconductor substrate; forming a first resist film on the film to be etched; forming a first opening and a second opening in the resist film, the second opening being located away from the first opening by a first distance; annealing the first resist film to make the first and second openings smaller; forming in the film to be etched a third opening and a fourth opening respectively corresponding to the first opening and the second opening that have been made smaller; removing the first resist film after the third opening and the fourth opening are formed in the film to be etched; forming a second resist film on the film to be etched; forming a fifth opening in a region of the second resist film corresponding to a position between the third and fourth openings; annealing the second resist film to make the fifth opening smaller; and forming in the film to be etched a sixth opening corresponding to the fifth opening.
In an embodiment of the present invention, the formation of the first and second openings in the first resist film and the formation of the fifth opening in the second resist film are performed by exposure and development using a single mask.
In another embodiment of the present invention, the distance between the first opening and the second opening is twice the diameter of the first opening or more.
According to still another aspect of the present invention, a fabrication method for a semiconductor device includes: forming a film to be etched on a semiconductor substrate; forming a first resist film on the film to be etched; forming a plurality of first openings in the first resist film; annealing the first resist film and then removing a part of the film to be etched that is exposed through the first openings; removing the first resist film and then forming a second resist film on the film to be etched including an area in which the film to be etched has been removed; forming a plurality of second openings in regions of the second film respectively corresponding to regions between adjacent two of the first openings; and annealing the second resist film and then removing a part of the film to be etched that is exposed through the second openings.
This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.
REFERENCES:
patent: 5776836 (1998-07-01), Sandhu
Furukawa Takamitsu
Kobayashi Shouzou
Muto Koki
Nara Akihiko
Nishimuro Tadashi
Frank Robert J.
Oki Electric Industry Co. Ltd.
Powell William A.
Venable
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