Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-12-03
2001-06-12
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S438000, C438S666000, C438S254000, C438S964000
Reexamination Certificate
active
06245633
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88119201, filed Nov. 4, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a capacitor of a semiconductor memory device. More particularly, the present invention relates to a fabrication method for a stacked capacitor of a dynamic random access memory (DRAM) device.
2. Description of the Related Art
As semiconductors enter the stage of the deep sub-micron manufacturing, the device dimensions continue to reduce; in another words, the allowable capacitor area becomes smaller in a DRAM device. The size of the software used in computers, on the other hand, is getting larger, the required memory capacity thus needs to be increased. With the demands of a continuous downsizing of the device dimension and an increase for the memory capacity, the conventional approach in fabricating a dynamic random access memory capacitor must be changed to accommodate the current trend of development of semiconductor devices.
Although a stacked capacitor is the major technique employed in the manufacturing for a conventional semiconductor capacitor, related research on stacked capacitor continues even the fabrication of semiconductors has entered the stage of deep sub-micro manufacturing.
Although a stacked capacitor, for example, the crown type, the fin type, the cylinder type or the spread type, can meet the demand of a highly integrated DRAM device, it is very difficult to use the stacked type capacitor for a 256 Mega or 1 Giga bit capacitor due to the limited design rule.
FIGS. 1A
to
1
E are schematic cross-sectional view showing the manufacturing of a double-sided stacked capacitor according to the prior art.
As shown in
FIG. 1A
, a substrate
100
, comprising devices, is sequentially covered with a silicon oxide layer
102
and a silicon nitride layer
104
. The silicon oxide layer
102
serves as an inter-layer dielectric (ILD), and the silicon nitride layer
104
is an etching stop layer during the formation of the double-sided crown structure of the capacitor.
Photolithography and etching are further conducted to define a contact opening
106
in the silicon oxide layer
102
and the silicon nitride layer
104
. A doped polysilicon plug
107
is further formed in the contact opening
106
.
Referring to
FIG. 1B
, an insulation layer
108
is then formed, covering the silicon nitride layer
104
and the polysilicon plug
107
. Photolithography and etching are further conducted to define an opening
110
in the insulation layer
108
, exposing the polysilicon plug
107
and a portion of the silicon nitride layer
104
.
As shown in
FIG. 1C
, a conformal amorphous silicon layer
112
is formed on the substrate
100
, covering the opening
110
.
Referring to
FIG. 1D
, using the insulation layer
108
as a polishing stop layer, the amorphous silicon layer
112
covering the surface of the insulation layer
108
is removed, leaving the remaining amorphous silicon layer
112
a
in the opening
110
.
Continuing to
FIG. 1E
, using the silicon nitride layer
104
as an etching stop layer, the insulation layer
108
covering the surface of the silicon nitride layer
104
is removed.
At this point, a capacitor with a crown structure is thus formed. A hemispherical grain polysilicon layer is then formed on the amorphous silicon layer
112
a
, followed by sequentially forming the dielectric layer of the capacitor and the upper electrode of the capacitor to complete the formation of a double-sided crown structured capacitor.
The capacitance of the capacitor formed according to the above prior art, however, can not meet the requirements of a 256M or 1G DRAM device.
SUMMARY OF THE INVENTION
Based on the foregoing, the present invention provides a fabrication method for a stacked capacitor, wherein a dielectric layer and an etching stop layer are formed on the substrate, and a contact plug is formed in the dielectric layer and the etching stop layer. After this, a first material layer is also formed on the etching stop layer and then patterned to form an opening which exposes a portion of the etching stop layer and the contact plug. A first amorphous silicon layer is then formed on the substrate, followed by forming and patterning a second material layer. Chemical dry etching is then conducted to remove a portion of the first amorphous silicon layer which covers the surface of the first material layer. The first amorphous silicon layer remaining on the sidewall and on the bottom of the opening forms a crown shaped amorphous silicon layer. A second amorphous silicon layer is then formed on the substrate, followed by performing anisotropic etching to form an amorphous silicon spacer. The second material layer and the first material layer are removed. Thereafter, a selective hemispherical grain polysilicon layer is formed on the exposed surfaces of the crown shaped amorphous silicon layer and the amorphous silicon spacer to form a bottom electrode with a double sided, double crown structure. Subsequently, a capacitor dielectric layer and an upper electrode are formed.
To increase the surface area of the bottom electrode according to the present invention is through the formation of a bottom electrode with a double-sided double crown structure. The memory capacity of the memory device is thereby increased.
The double-sided double crown structured bottom electrode of the present invention is formed by a crown shaped amorphous silicon layer and an amorphous silicon spacer.
The fabrication method for a stacked capacitor according to the present invention only applies the typical deposition, photolithography and etching techniques to achieve the purpose of increasing the memory capacity of a memory device. Since the more expensive chemical mechanical polishing process is not required for the fabrication method of the present invention and the process window is greater, the method of the present invention is simpler and the manufacturing cost is lower.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 06021390A (1994-01-01), None
Bowers Charles
Huang Jiawei
Huynh Yennhu B.
J.C. Patents
Taiwan Semiconductor Manufacturing Co. Ltd.
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