Fabrication method for a chip packaging structure

Details Fabrication method for a chip packaging structure Fabrication method for a chip packaging structure

2008-01-22

2008-01-22

Geyer, Scott B. (Department: 2812)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C257SE21499

Reexamination Certificate

active

07320901

ABSTRACT:
A fabrication method for a chip packaging structure disclosed herein is utilizing the method of plating metal to connect different layers so as to replace the traditional method that drill hole firstly and then plate metal in the hole. In the present invention, the metal in the conductive through hole is solid metal so as can provide good ability of heat sinking. Besides, the present fabrication method utilizes the existing manufacturing processes without extra process or equipment so as can decrease the PCB processes and lower the package cost.

REFERENCES:
patent: 2005/0153483 (2005-07-01), Groenhuis et al.

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