Fabrication method for a buried bit line

Details Fabrication method for a buried bit line Fabrication method for a buried bit line

2000-05-09

2001-08-21

Neims, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

C438S253000, C438S396000

Reexamination Certificate

active

06277717

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication method for a memory device. More particularly, the present invention relates to a fabrication method for a buried bit line.
2. Description of the Related Art
The escalating demand of a higher integration in semiconductor devices has led to the development of devices with sub-micron features. Smaller features allow the reduction in the performance degrading capacitance and resistance. In addition, smaller features would result in smaller chips, while maintaining the same level of integration that is acquired for semiconductor chips fabricated with the larger features. As a result, a greater number of the denser, smaller chips can be obtained from a specific substrate size. Thus, a lower manufacturing cost is obtained for an individual chip.
A memory device, for example, a typical DRAM cell, is comprised of a capacitor structure, overlying a transfer gate transistor and connecting to the source or a drain region of the transfer gate transistor. The bit line of the DRAM cell is usually comprised of a metal line traversing an insulator layer and contacting a source or a drain region of the transfer gate through a contact hole in the insulator layer. However, for these structures to be all formed in a DRAM cell, design rules for minimizing area and ensuring adequate process margin are required.
FIGS. 1A
to
1
D are schematic cross-sectional views showing the manufacturing of a conventional DRAM cell. As shown in
FIG. 1A
, a shallow trench isolation (STI) structure
102
is formed in a substrate
100
. A plurality of word lines
104
is formed over the substrate
100
and the STI structure
102
. A plurality of source/drain regions
106
are formed in the substrate
100
between the word lines
104
. An insulation material is deposited over the word lines
104
and into the space between the word lines to form an insulation layer
108
.
Referring to
FIG. 1B
, photolithography and etching operations are conducted to form the contact openings
110
in the insulation layer
108
. The contact openings
110
expose portions of the source/drain regions
106
. Conductive material is then deposited into the openings
110
and over the insulation layer
108
. The conductive layer is patterned to form the landing pads
112
. An insulation layer
114
is subsequently from on the resultant structure.
As shown in
FIG. 1C
, photolithography and etching operations are carried out to form a bit line opening
116
in the insulation layer
114
. The bit line opening
116
exposes a portion of the landing pad
112
. A conductive material is then deposited on the insulation layer
114
, filling the bit line opening
116
. The conductive material is then patterned to form the bit line
118
, which is electrically connected to the landing pad
112
. An insulation layer
120
is further formed over the insulation layer
114
and the bit line
118
.
Continuing to
FIG. 1D
, node contact openings
122
are formed in the insulation layer
120
. The node contact openings
118
expose a portion of the landing pad
112
not yet electrically connected to the bit line. A node contact
124
is formed inside each node contact openings
122
. Capacitors (not shown in Figure) are subsequently formed above the substrate
100
to complete the fabrication of a DRAM cell.
In the aforementioned process, the node contact openings
122
are formed after a structure of multiple conductive layers (including word lines and bit lines) isolated from each other by a plurality of insulation layers (
108
,
114
and
120
) is formed. Consequently, there is a considerable height difference between a peripheral circuit region and a device region in a silicon chip. This often leads to a subsequent planarization problem. Additionally, as the level of device integration continues to increase, the node contact openings formed after the bit line have a bigger aspect ratio. With a big aspect ratio, the node contact openings
122
are more difficult to form, resulting in a node contact
124
with a low conductivity. Hence, the electrical contact of the node contact
124
is poor. Furthermore, with an increased integration for the integrated circuit, the problem of misalignment becomes more significant. The node contact openings (
206
as illustrated in
FIG. 2
) are typically formed near the cross-section between the word lines and the bit lines. It is thus a great challenge to secure the alignment margin when forming the node contact openings. Therefore, if a misalignment occurs during the contact opening formation, the node contact opening may expose the bit line or word line. When a doped polysilicon layer is subsequently deposited in the contact opening makes contact with the exposed bit line or word line, an electrical short circuit and a damage to the semiconductor device may result.
SUMMARY OF THE INVENTION
Based on the foregoing, a method to fabricate a memory device comprising a buried bit line is provided. According to this version of the present invention, a substrate comprising a plurality of word lines formed thereon is provided. A first insulation layer, for example, a dielectric layer, is formed over the substrate, covering the word lines. A node landing pad is formed in the first insulation layer, wherein the node landing pad is covered with a second insulation layer of a first thickness. A bit line contact is then formed in the first insulation layer, and the bit line contact is covered with a third insulation layer of a second thickness, wherein the second thickness is greater than the first thickness. A trench is further formed in the first insulation along the sides of the bit line contact and is extended across the first insulation layer. After this, a conductive material partially fills the trench to form a borderless buried bit line. A fourth insulation layer with a third thickness is further deposited to fill the remaining space in the trench, wherein the third thickness is greater than the first thickness. Thereafter, a planarization procedure is conducted on the surface of the first insulation layer to remove the second insulation layer, exposing the node landing pad. A bottom electrode is subsequently formed on the exposed landing pad.
According to this version of the present invention, the node contact opening is formed before the formation of the bit line. The difficulty in securing an alignment margin for the node contact opening formed at the cross-section between the bit lines and the word lines is mitigated. Furthermore, the node landing pad and the buried bit line are covered by insulation materials. The potential problem of a misalignment when forming the bottom electrode and the buried bit line, respectively, leading to the exposure of the conductive units and a subsequent electrical short circuit are thus revented.
Additionally, the buried bit line and the node landing pads are embedded in the came insulation layer, the number of dielectric layers is reduced. Moreover, the node contact opening has a smaller aspect ratio. When the node landing pad is formed in the node contact opening, a better step coverage of the conductive layer is obtained. Since both the bit lines and the node contacts are embedded in the first insulation layer, a planarized surface is thus provided to facilitate the subsequent manufacturing processes.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5102814 (1992-04-01), Woo
patent: 5369048 (1994-11-01), Hsue
patent: 5753551 (1998-05-01), Sung

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