Fabrication method and device structure of shallow trench...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S429000, C438S430000, C438S431000, C438S432000, C438S435000, C438S492000, C438S503000, C438S504000, C438S507000

Reexamination Certificate

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07029988

ABSTRACT:
A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.

REFERENCES:
patent: 5266813 (1993-11-01), Comfort et al.
patent: 5308785 (1994-05-01), Comfort et al.
patent: 5994178 (1999-11-01), Wu
patent: 6251746 (2001-06-01), Hong et al.
patent: 6399970 (2002-06-01), Kubo et al.
patent: 6537894 (2003-03-01), Skotnicki et al.
patent: 6583000 (2003-06-01), Hsu et al.
patent: 6600170 (2003-07-01), Xiang
patent: 6673696 (2004-01-01), Arasnia et al.
patent: 6696348 (2004-02-01), Xiang
patent: 6724008 (2004-04-01), Fitzergald
patent: 6825086 (2004-11-01), Lee et al.
patent: 6846720 (2005-01-01), Balasubramanian et al.
patent: 6861316 (2005-03-01), Hara et al.
patent: 2003/0013305 (2003-01-01), Sugii et al.
patent: 2003/0049893 (2003-03-01), Currie et al.
patent: 2004/0009636 (2004-01-01), Ichinose et al.
patent: 2004/0029355 (2004-02-01), Hara et al.
patent: 2004/0036142 (2004-02-01), Shima
patent: 2004/0087107 (2004-05-01), Takenaka
patent: 2004/0142537 (2004-07-01), Lee et al.
patent: 2004/0164373 (2004-08-01), Koester et al.
patent: 2004/0173812 (2004-09-01), Currie et al.
patent: 2004/0180509 (2004-09-01), Wang et al.
patent: 2004/0256634 (2004-12-01), Sugihara et al.
patent: 0 552 671 (1993-01-01), None
Wolf, Jr. Ph.D., Stanley and Richard N. Tauber, Ph.D., “Thermal Oxidation of Single Crystal Silicon,” Silicon Processing for the VLSI Era—vol. 1: Process Technology, Lattice Press, 1986, p. 198.
K. Rim, S. Koester, M. Hargrove, J. Chu, P.M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill, H-S. P. Wong, “Strained Si NMOSFETs for High Performance CMOS Technology”, 2001 Symposium on VLSI Technology Digest of Technical Papers, pp. 59-60.

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