Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2005-04-12
2005-04-12
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S429000, C438S430000, C438S431000, C438S432000, C438S435000, C438S492000, C438S503000, C438S504000, C438S507000
Reexamination Certificate
active
06878606
ABSTRACT:
A method and device are provided for shallow trench isolation for a silicon wafer containing silicon-germanium. In one example, the method comprises forming a trench region in a silicon-germanium layer of a semiconductor substrate containing a single crystal silicon-germanium layer on the surface; forming a first single crystal silicon layer in the trench region and an active region; oxidizing the first single crystal silicon layer; forming a first thermal oxide layer on the surface of the first single crystal silicon layer; forming a device isolation region; embedding an insulator in the trench region; and forming a device in an active region over the single crystal silicon-germanium layer separated by the device isolation region, wherein the step of forming the device in the active region further includes forming a doped region of a depth to reach within the single crystal silicon-germanium layer below the first single crystal silicon layer.
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K. Rim, S. Koester, M. Hargrove, J. Chu, P.M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. Ieong, A. Grill, H-S. P. Wong, “Strained Si NMOSFETs for High Performance CMOS Technology”, 2001 Symposium on VLSI Technology Digest of Technical Papers, pp. 59-60.
Ohnishi Kazuhiro
Onai Takahiro
Sugii Nobuyuki
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Reed Smith LLP
Renesas Technology Corp.
Thomas Toniae M.
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