Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Warping of semiconductor substrate
Reexamination Certificate
2007-04-03
2007-04-03
Lee, Calvin (Department: 2818)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Warping of semiconductor substrate
C257S724000
Reexamination Certificate
active
11080284
ABSTRACT:
The present invention provides for a common substrate with multiple sections, each constituting a separate layer of a memory device. Fold lines are arranged on the substrate to define separate sections and to provide a means for folding the sections on each other to form a multiple-layer memory device. In one application, a substrate has a fold line formed by alterations to the substrate material to form a fold line on the substrate. A first conductor section is formed with an array of parallel conductors or wires spaced across the section. A second section on the common substrate has an array of parallel conductors or wires spaced across the second section, the conductors being perpendicular to the conductors on the first section. The first and second sections are folded along the fold line over on top of each other, after a semiconductor layer has been deposited on one or both of the conductor layers, thereby forming a matrix of memory cells. The fold line is formed by removal of some of the material, such as by perforations or depressions, by deforming the material, such as by creasing, or by altering a property of the material, such as by changing the strength or flexibility of the substrate material.The conductors or the first section may also be fabricated with narrowing cross-section areas at points where fuses are to be set to an open circuit.
REFERENCES:
patent: 5776797 (1998-07-01), Nicewarner et al.
patent: 6007888 (1999-12-01), Kime
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6121676 (2000-09-01), Solberg
Perlov Craig M
Schantz Christopher A
Hewlett--Packard Development Company, L.P.
Lee Calvin
LandOfFree
Fabrication and assembly structures and methods for memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication and assembly structures and methods for memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication and assembly structures and methods for memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3729271