Fabricating T-gate MESFETS employing double exposure, double dev

Details Fabricating T-gate MESFETS employing double exposure, double dev Fabricating T-gate MESFETS employing double exposure, double dev

1988-12-22

1990-09-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 39, 437175, 437203, 437229, 437912, 437944, 437179, H01L 21338

Patent

active

049593269

ABSTRACT:
A method for forming a T-gate for a MESFET device comprises a double exposure, double develop process. In a first exposure employing lithography a layer of PMMA is applied first to a substrate and spun to a desired thickness and then baked for a predetermined period. The gate pattern was aligned to the ohmic level and either E-beam written or exposed to deep UV radiation through a quartz mask. The wafer as treated was then spray developed using a mixture of MIBK and alcohol. After coating with a Novolak resist, the same gate mask was either realigned to the Ohmic level and exposed to mid-range UV radiation in the 400 nm range or alternatively E-beam written with a modified gate pattern to eliminate the T at the gate pad. The wafer was then spray developed again, this time using LSI developer. The second photo was overexposed in order to form a large opening through the top of the T while the first photo was underexposed to make the stem of the T as narrow as possible. After an oxygen plasma descum, the wafer was spray etched with a suitable solution and then rinsed. The resultant wafer possessed a T-shaped recess for the gate configuration which then was conventionally metallized to form MESFETS.

REFERENCES:
patent: 4213840 (1980-07-01), Omori et al.
patent: 4532005 (1985-07-01), Grieco et al.
patent: 4557797 (1985-12-01), Fuller et al.
patent: 4621042 (1986-11-01), Pampalone et al.
patent: 4657629 (1987-04-01), Bigelow
patent: 4774193 (1988-09-01), Juergens
Taylor, G. C. et al., "High-Efficiency . . . ", IEEE Transaction on Electron Devices, vol. ED-34, No. 6, Jun. 1987, pp. 1259-1263.
Chao, P. C. et al., "Electron-Beam Fabrication . . . ", IEEE Transaction on Electron Devices, vol. ED-32, No. 6, Jun. 1985, pp. 1042-1046.
Bandy, S. G. et al., "Submicron GaAs . . . ", IEEE Electron Device Letters, vol. EDL-4, No. 2, Feb. 1983, pp. 42-44.
Mueller, K. H. et al., "Synchrotron Lithography . . . ", Proceedings of Microcircuit Engineering, 1986, 8 pages.
Morimoto, H. et al., "A GaAs Metal-Semiconductor . . . ", J. Vac. Sci. Technol. B 5(1), Jan./Feb. 1987, pp. 211-214.
Matsumura, M. et al., "Submicrometer Lift-Off . . . ", Electronics Letters, Jun. 11, 1981, vol. 17, No. 12, pp. 429-430.

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