Fabricating substrates having low inductance via arrangements

Details Fabricating substrates having low inductance via arrangements Fabricating substrates having low inductance via arrangements

2006-02-16

2009-11-10

Nguyen, Donghai D. (Department: 3729)

Metal working

Method of mechanical manufacture

Electrical device making

C029S846000, C257S774000, C716S030000, C716S030000

Reexamination Certificate

active

07614141

ABSTRACT:
A low inductance via arrangement for multilayer ceramic (MLC) substrates is provided. With the MLC substrate and via arrangement of the illustrative embodiments, the via-field inductance for a given contact pad array is reduced. This reduction is achieved by the introduction of T-jogs and additional vias. These T-jogs and additional vias form additional current paths that cause additional parallel inductances that reduce the via-field inductance. In one illustrative embodiment, the additional T-jogs and vias are added to a center portion of a contact pad array. The T-jogs are comprised of two jogs in a wiring layer of the MLC, each jog being toward a via associated with an adjacent contact pad in the contact pad array. These additional T-jogs and vias form additional current loops parallel to the existing ones which thus, reduce the total inductance of the via-field.

REFERENCES:
patent: 5292624 (1994-03-01), Wei
patent: 6417463 (2002-07-01), Cornelius et al.
patent: 6617243 (2003-09-01), Weekly
patent: 1111969 (2001-06-01), None

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