Fabricating semiconductor chips

Details Fabricating semiconductor chips Fabricating semiconductor chips

2005-12-13

2005-12-13

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C438S401000

Reexamination Certificate

active

06975040

ABSTRACT:
A semiconductor chip and method of fabrication which permits precise location of hidden areas of the chip. At least two alignment marks are formed in or on the top passivation layer to provide topological features for location of the hidden areas. The hidden areas can then be selectively etched and/or added to, for example, by a focused ion beam for repair or other functions.

REFERENCES:
patent: 5346858 (1994-09-01), Thomas et al.
patent: 6278193 (2001-08-01), Coico et al.
patent: 6392300 (2002-05-01), Koike
patent: 6465898 (2002-10-01), Hnilo et al.
patent: 1-241116 (1989-09-01), None
patent: 2001-7274 (2001-01-01), None

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