Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2011-07-19
2011-07-19
Landau, Matthew C (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257SE21503
Reexamination Certificate
active
07981725
ABSTRACT:
A fabricating process of a chip package structure is provided. First, a first substrate having a plurality of first bonding pads and a second substrate having a plurality of second bonding pads are provided, wherein bumps are formed on the first bonding pads of the first substrate. A first two-stage adhesive layer is formed on the first substrate and is B-stagized to form a first B-staged adhesive layer. A second two-stage adhesive layer is formed on the second substrate and is B-stagized to form a second B-staged adhesive layer. Then, the first substrate and the second substrate are bonded via the first and second B-staged adhesive layer such that the bumps pierce through the second B-staged adhesive layer and are electrically connected to the second bonding pads, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps.
REFERENCES:
patent: 6168972 (2001-01-01), Wang et al.
patent: 6252301 (2001-06-01), Gilleo et al.
patent: 6311888 (2001-11-01), Funada et al.
patent: 6410415 (2002-06-01), Estes et al.
patent: 7579211 (2009-08-01), Ohuchi
patent: 7683482 (2010-03-01), Nishida et al.
patent: 2001/0051392 (2001-12-01), Akram
patent: 2003/0049425 (2003-03-01), Ono et al.
patent: 2004/0101991 (2004-05-01), Hiatt et al.
patent: 2004/0185601 (2004-09-01), Stepniak et al.
patent: 2005/0116353 (2005-06-01), Fujitani et al.
patent: 2005/0212131 (2005-09-01), Kawai
patent: 2005/0221532 (2005-10-01), Chee
patent: 2007/0148817 (2007-06-01), Williams et al.
patent: 2007/0215992 (2007-09-01), Shen et al.
patent: 2008/0044951 (2008-02-01), Bang et al.
patent: 1956179 (2007-05-01), None
Chinese First Examination Report of China Patent Application No. 200810214686.9, dated Apr. 16, 2010.
Shen Geng-Shin
Wang David Wei
ChipMOS Technologies (Bermuda) Ltd.
ChipMOS Technologies Inc.
Crawford Latanya
J.C. Patents
Landau Matthew C
LandOfFree
Fabricating process of a chip package structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabricating process of a chip package structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabricating process of a chip package structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2702030