Fabricating of a CMOS FET with reduced latchup susceptibility

Details Fabricating of a CMOS FET with reduced latchup susceptibility Fabricating of a CMOS FET with reduced latchup susceptibility

1985-05-10

1986-10-28

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29576E, 29576W, 148175, 148187, H01L 21365

Patent

active

046190333

ABSTRACT:
A method for forming a CMOS FET structure includes the steps of forming an apertured insulating layer on a silicon substrate and epitaxially forming a monocrystalline silicon island of first conductivity type through an aperture therein. The exposed surface of the silicon island is then thermally oxidized and the portion of the insulating layer not covered by the oxide is removed. A monocrystalline silicon island of second conductivity type is then formed adjacent to the oxidized silicon island of first conductivity type.

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