Fabricating an integrated circuit device having a vertical pnp t

Details Fabricating an integrated circuit device having a vertical pnp t Fabricating an integrated circuit device having a vertical pnp t

1985-03-18

1987-02-10

Roy, Upendra

Metal working

Method of mechanical manufacture

Electrical device making

29571, 29576B, 29576E, 29576W, 29578, 29589, 29591, 148 15, 148175, 148DIG10, 357 33, 357 34, 357 44, 357 50, H01L 2174, H01L 21265

Patent

active

046414193

ABSTRACT:
A process for producing semiconductor devices with a high-performance vertical pnp transistor having a high h.sub.fe and a high f.sub.T, comprising a step for forming an impurity region of a high concentration in a portion of a p-type buried layer and for increasing the concentration in a diffusion layer for isolation, a step for forming an n-type well region that reaches the p-type buried layer and that serves as a base of the vertical pnp transistor, and a step for forming an emitter of the vertical pnp transistor in a portion of said n-type well region, and for forming a collector electrode contact portion of the vertical pnp transistor, said contact portion reaching said impurity region of high concentration, by introducing p-type impurities into a portion of the p-type buried layer that serves as a portion of the collector of the vertical pnp transistor and into the p-type diffusion layer that works as an isolation layer or channel stop layer.

REFERENCES:
patent: 3930909 (1976-01-01), Schmitz et al.
patent: 3956035 (1976-05-01), Herrmann
patent: 4412376 (1983-11-01), De Bar et al.
patent: 4485552 (1984-12-01), Magdo et al.
patent: 4495010 (1985-01-01), Kranzer
patent: 4550491 (1985-11-01), Depey

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