Fabricating a single level merged EEPROM cell having an ONO memo

Fishing – trapping – and vermin destroying

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437 49, 437195, 437978, H01L 2176, H01L 21265

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active

051206722

ABSTRACT:
An electrically, programmable read-only memory cell is formed at a face (10) of a semiconductor layer (12). This cell comprises a doped drain region (36) and a doped source region (38) that are spaced from each other by a gate region (40). An ONO memory stack (28) is formed to extend over a portion of the gate region (40) that adjoins the drain region (36). The memory stack (28) is substantially spaced from the source region (38). A select gate insulator layer (30) is formed over the remainder of the gate region (40), and is preferably of the same thickness as the memory stack (28). A suitable gate conductor (32) is then deposited over insulator layers (26, 30). By being substantially spaced from source region (38), the memory stack (28) of the invention avoids the formation of ONO hole traps.

REFERENCES:
patent: 3719866 (1973-03-01), Naber et al.
patent: 3877055 (1975-04-01), Fisher et al.
patent: 4385308 (1983-05-01), Uchida
patent: 4611308 (1986-09-01), Lonky
patent: 4654828 (1987-03-01), Hagiwara et al.
patent: 4795719 (1989-01-01), Eitan
Chan et al., "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device" IEEEE Electron Device Letters, vol. EDL-8, No. 3, Mar. 1987, pp. 93-95.

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