Fabricating a CMOS transistor having low threshold voltages usin

Details Fabricating a CMOS transistor having low threshold voltages usin Fabricating a CMOS transistor having low threshold voltages usin

1985-01-09

1987-11-03

Roy, Upendra

Fishing, trapping, and vermin destroying

148DIG82, 357 42, 357 67, 437 57, 437200, H01L 21265, H01L 2128

Patent

active

047035528

ABSTRACT:
The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.

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