Extremely small area npn lateral transistor

Details Extremely small area npn lateral transistor Extremely small area npn lateral transistor

1987-06-24

1991-08-27

Carroll, J.

357 55, H01L 2972, H01L 2906

Patent

active

050437879

ABSTRACT:
An array of hundreds of devices may be simultaneously processed on a chip to sub-micron dimensions by establishing tiny active regions for each transistor surrounded by field oxide filled moats or slotted regions, wherein the slots are utilized to dope the substrate within the active region. The N type substrate is double energy boron planted through one surface to establish a P region to a given depth. This surface is oxidized and photoresist mask conventionally to open regions for the slots which are ion milled or ODE etched to a given depth. N+ regions are established by the slots by ion implanting at an angle such that the entire depth of the slot is not doped but rather the doping is confined to a region within the double energy P implanted depth. Drive-in diffusion enlarges the N+ areas for the emitter and collector and oxidation fills the moat insulating regions around the active area. The oxide is stripped and the P region enhanced to P+ at the surface, with silox being deposited and opened for metal contacts to the P+ region for the base and the emitter and collector region. The doping profile of the base region provides a potential barrier to minimize the flow of electrons toward the surface because the emitter electrons are channeled through the less heavily doped part of the base region to the collector.

REFERENCES:
patent: 4519849 (1985-05-01), Korsh et al.
patent: 4641170 (1987-02-01), Ogura et al.
S. A. Evans et al., "A 1-Micron Bipolar VLSI Technology", IEEE Transactions On Electron Devices, vol. ED-27 (Aug. 1980) pp. 1373-1379.
S. Konaka et al., "A 30-ps Si Bipolar DC Using Super Self-Aligned Process Technology", IEEE Transactions on Electron Devices, vol. ED-33, No. 4 (Apr. 1986), pp. 526-531.

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