Extreme level circuit

Details Extreme level circuit Extreme level circuit

1990-11-30

1992-10-27

Laroche, Eugene R.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307351, 307362, H03K 522, H03K 5153

Patent

active

051592118

ABSTRACT:
An extreme level circuit for detecting an extreme level of two input signals. The circuit includes a differential circuit wherein a pair of differential transistors are connected their emitters with each other and a common current source is connected to the emitter junction node of the differential transistors, a pair of emitter follower transistors coupled to the differential circuit for applying the input signals to the bases of the differential transistors and a pair of bias generating circuits each coupled in series with one of the emitter follower circuits, wherein each bias generating circuit has a bias transistor whose base is connected to a fixed bias source and a current source connected in series with the bias transistor, and wherein the pair of bias generating circuits are cross connected to the collectors of the differential transistors.

REFERENCES:
patent: Re30839 (1981-12-01), Miyamoto
patent: 3925719 (1975-12-01), Rodi
patent: 4387309 (1983-06-01), Shacter
patent: 4625131 (1986-11-01), Kasperkovitz et al.
patent: 4760286 (1988-07-01), Pigott
patent: 4811100 (1989-03-01), Umezawa
patent: 4968904 (1990-01-01), Yamashita et al.
patent: 5017805 (1991-05-01), Kase
patent: 5038055 (1991-08-01), Kinoshita

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