Extraction of interconnect parasitics

Details Extraction of interconnect parasitics Extraction of interconnect parasitics

2002-08-08

2004-11-16

Nguyen, Vincent Q. (Department: 2858)

Electricity: measuring and testing

Impedance, admittance or other quantities representative of...

Lumped type parameters

C324S076540, C324S677000, C331S057000

Reexamination Certificate

active

06819123

ABSTRACT:

FIELD OF INVENTION
This invention relates to improvements in the extraction of interconnect parasitics.
BACKGROUND OF INVENTION
Previously capacitance and resistance interconnect parasitics have been extracted from specific test structures. This is complex and time consuming. A direct capacitance extraction parametric tester can measure parallel plate and comb structure capacitance. Such a measurement tool capability and Device Under Test (DUT) area, limit accuracy and scribeline implementation. An alternative method that has been used is to load a ring oscillator with appropriate metalization, then to measure the frequency of the output. The ring oscillator capacitance extraction uses the ring oscillator frequency difference between a reference ring oscillator and one containing the resistance and capacitance (RC) network to calculate the capacitance. The ring oscillator frequency is the sum of the ring oscillator gate and the RC delays. This has various advantages, especially that of more reasonably simulating actual parasitic conditions in a circuit. However, the technique does not give a good overall value of just the parasitics.
The method used previously has two independent ring oscillators, one with minimal loading, and the other with significant parasitic loading. From this it is possible to obtain two delay times, and to calculate the delay attributable to the parasitics. This can cause some problems, since ring oscillators from a wafer lot can, under normal temperature and voltage conditions, display output frequencies that can range over +/−30% from normal. Adjacent rings would be unlikely to exhibit such large variation, but a 10% difference is not uncommon. Since the delay time of the parasitics is rarely greater than the delay of the ring, any delay in the ring causes a similar error in the parasitic values. An example of this type of circuit is shown in
FIGS. 1 and 2
.
FIG. 1
illustrates a conventional layout of four ring oscillators
11
-
14
. Sharing certain common bondpads this requires 12 bondpads
40
(four output pads, four voltage supply, two shared ground pads, and two divider supply pads) for four rings. Each ring has an associated divider. FIG.
2
(
a
) illustrates a minimum interconnect ring of 11 inverter
20
-
30
oscillator, with frequency divider
31
. FIG.
2
(
b
) illustrates the same structure but with additional interconnect
33
. The additional interconnect has parasitic capacitance and resistance that slows down the ring frequency.
SUMMARY OF INVENTION
In accordance with one embodiment of the present invention an improved detectability of the effects of interconnect RC in a logic circuit is provided by multiplexing parasitic and minimum oscillator circuitry to obtain delay with and without parasitics.


REFERENCES:
patent: 6005829 (1999-12-01), Conn

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