Static information storage and retrieval – Floating gate
Reexamination Certificate
2003-02-11
2004-12-28
Young, Brian (Department: 2819)
Static information storage and retrieval
Floating gate
C365S185260
Reexamination Certificate
active
06836430
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the storing, in an integrated circuit, of an unchangeable binary code. The present invention more specifically relates to the extracting, from an integrated circuit, of a binary code resulting from parameters linked to the manufacturing of this circuit. Such parameters linked to the manufacturing are generally called physical parameters and are then provided by a physical parameter network (PPN). Such an “embedded” binary code is used in an integrated circuit, for example, to avoid its permanent storage in the form of a digital word in a register or the like and to prevent detection of this code. In an application to the identification of an electronic element or assembly based on parameters linked to the manufacturing of an identification circuit contained in an integrated circuit chip, this identification is currently designated as an “integrated circuit fingerprint”.
2. Discussion of the Related Art
The present invention more specifically relates to the extraction of a binary code stored in the form of at least partially resistive electric paths and interpreted by flip-flops or the like. Example of circuits for storing such binary codes and of identification of an integrated circuit chip by such codes are described in French patent applications No. 01/04583 and 01/04585 of the assignee, which are incorporated herein by reference.
The principle used by these circuits is to have a same electric edge triggering a reading circulate in different electric paths reaching different flip-flops. According to whether the delay of a given path is shorter or longer than a reference or average delay synchronizing the flip-flop reading, the output state of the corresponding flip-flop is 0 or 1. The outputs of the different flip-flops then provide the binary code stored in the form of electric paths. These electric paths can be made different simply by the length of the tracks forming them, but it is preferable for them to contain a resistive element (in practice associated with a capacitive element formed of the gates of MOS transistors forming the flip-flops) to form an RC cell.
An important advantage of such a binary code storage is that it is stored, not directly in digital form, but, in a way, in analog form, which makes its piracy more difficult.
In the above-mentioned circuits, to fulfill the aim of making the code stored by the electric paths invisible, it must be ascertained that the paths are not too different (in terms of length) as compared to the electric path providing the reference delay. In the opposite case, there is a risk of enabling optical detection according to whether the path is obviously longer or shorter than the reference path.
Further, in some cases and in a perfectly random and unpredictable manner, an electric path of one of the flip-flops may, when associated with the propagation of the edge in this flip-flop, exhibit exactly the same delay as the average path. There then is a risk, for this flip-flop, to have a non-reproducible output state from one extraction to another of the binary code.
These two imperfections of the above-mentioned storage circuits are due to the use of an average delay to synchronize the flip-flop reading.
SUMMARY OF THE INVENTION
The present invention aims at improving the extraction of a binary code embedded in an integrated circuit.
The present invention also aims at providing a circuit for storing a binary code originating from physical parameters of an integrated circuit, which overcomes the disadvantages of the above-mentioned circuits. More specifically, the present invention aims at avoiding the use of a common reference or average electric path to compare the electric paths associated with the different flip-flops.
The present invention also aims at making the delays introduced by the different electric paths of such a circuit undetectable.
The present invention also aims at providing a solution which is compatible with the technology currently used to form MOS transistors and which, in particular, generates no additional manufacturing step.
To achieve these and other objects, the present invention provides an integrated cell for extracting a binary value based on a propagation of an edge of a triggering signal in two electric paths, comprising across two terminals of application of a voltage, two parallel branches each comprising, in series:
a resistor for differentiating the electric paths;
a read transistor, the junction point of the resistor and of the read transistor of each branch defining an output terminal of the cell, and the gate of the read transistor of each branch being connected to the output terminal of the other branch; and
a selection transistor.
According to an embodiment of the present invention, the resistors are made of polysilicon and are sized to have identical nominal values.
According to an embodiment of the present invention, the cell is associated with a circuit for reading an initial state of the cell and for stabilizing this state by causing a stable and irreversible decrease, in the cell read operating current range, of the value of the resistance associated with the branch outputting a high state.
According to an embodiment of the present invention, said value decrease is caused by temporarily imposing, in the corresponding resistor, the flowing of a current which is greater than the current for which the value of the resistance is maximum.
According to an embodiment of the present invention, each branch further comprises a stabilization transistor connecting its output terminal to said terminal of application of a voltage opposite to that to which the resistor of the involved branch is connected.
According to an embodiment of the present invention, the stabilization transistors are used to cause said decrease in the value of one of the resistors.
According to an embodiment of the present invention, said voltage is chosen between a relatively low read voltage and a relatively high voltage of stabilization of the initial cell state.
According to an embodiment of the present invention, said transistors are N-channel MOS transistors.
According to an embodiment of the present invention, said transistors are P-channel MOS transistors.
According to an embodiment of the present invention, said resistor for differentiating the electric paths are passive resistors.
The present invention also provides a method for controlling the stabilization of the value of a cell, comprising the steps of:
causing the reading of an initial state of the cell; and
temporarily submitting the resistor which is associated with the branch providing a high output state, to a constraint current greater than a current for which the value of the resistance exhibits a maximum.
According to an embodiment of the present invention, the constraint current is selected from a predetermined table of correspondence between the constraint current and the desired final resistance.
The present invention also provides a circuit for storing and extracting a binary code over n bits in and from an integrated circuit chip, comprising:
n integrated cells of extraction of a binary value; and
a central control unit.
According to an embodiment of the present invention, the n bits contained in the cells are extracted in parallel.
The present invention also provides a circuit for identifying an integrated circuit chip comprising a binary code storage and extraction circuit.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 3636530 (1972-01-01), Mark et al.
patent: 3911368 (1975-10-01), Tarczy-Hornoch
patent: 4023110 (1977-05-01), Oliver
patent: 5608645 (1997-03-01), Spyrou
patent: 5686850 (1997-11-01), Takaki et al.
patent: 6122191 (2000-09-01), Hirose et al.
patent: 6363011 (2002-03-01), Hirose et al.
patent: 2001/0050952 (2001-12-01), Nikutta
patent: 0 863 546 (1998-09-01), None
pate
Bardouillet Michel
Malherbe Alexandre
Wuidart Luc
Jorgenson Lisa K.
McClellan William R.
Nguyen John B
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
LandOfFree
Extraction of a binary code based on physical parameters of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Extraction of a binary code based on physical parameters of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Extraction of a binary code based on physical parameters of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3304813