Electric lamp or space discharge component or device manufacturi – Process – With assembly or disassembly
Reexamination Certificate
2001-05-18
2002-03-26
Ramsey, Kenneth J. (Department: 2879)
Electric lamp or space discharge component or device manufacturi
Process
With assembly or disassembly
Reexamination Certificate
active
06361392
ABSTRACT:
TECHNICAL FIELD
This invention relates in general to visual displays for electronic devices, and in particular to an improved extraction grid for displays.
BACKGROUND OF THE INVENTION
FIG. 1
is a simplified side cross-sectional view of a portion of a display
10
including a faceplate
20
and a baseplate
21
in accordance with the prior art.
FIG. 1
is not drawn to scale. The faceplate
20
includes a transparent viewing screen
22
, a transparent conductive layer
24
and a cathodoluminescent layer
26
. The transparent viewing screen
22
supports the layers
24
and
26
, acts as a viewing surface and as a wall for a hermetically sealed package formed between the viewing screen
22
and the baseplate
21
. The viewing screen
22
may be formed from glass. The transparent conductive layer
24
may be formed from indium tin oxide. The cathodoluminescent layer
26
may be segmented into pixels yielding different colors for color displays. Materials useful as cathodoluminescent materials in the cathodoluminescent layer
26
include Y
2
O
3
:Eu (red, phosphor P-56), Y
3
(Al, Ga)
5
O
12
:Tb (green, phosphor P-53) and Y
2
(SiO
5
):Ce (blue, phosphor P-47) available from Osram Sylvania of Towanda PA or from Nichia of Japan.
The baseplate
21
includes emitters
30
formed on a planar surface of a semiconductor substrate
32
. The substrate
32
is coated with a dielectric layer
34
. In one embodiment, this is effected by deposition of silicon dioxide via a conventional TEOS process. The dielectric layer
34
is formed to have a thickness, measured in a direction perpendicular to a surface of the substrate
32
as indicated by direction arrow
36
, that is less than a height of the emitters
30
. An extraction grid
38
comprising a conductive material is formed on the dielectric layer
34
. The extraction grid
38
may be realized, for example, as a thin layer of polysilicon. The radius of an opening
40
created in the extraction grid
38
, which is also approximately the separation of the extraction grid
38
from the tip of the emitter
30
, is about 0.4 microns, although larger or smaller openings
40
may also be employed. This separation is defined herein to mean being “in close proximity.”
Another dielectric layer
42
is formed on the extraction grid
38
. A chemical isolation layer
44
, such as titanium, is formed on the dielectric layer
42
. A high atomic mass layer
46
, such as tungsten, is formed on the chemical isolation layer
44
for reasons that will be explained below.
The baseplate
21
also includes a field effect transistor (“FET”)
50
formed in the surface of the substrate
32
for controlling the supply of electrons to the emitter
30
. The FET
50
includes an n-tank
52
formed in the surface of the substrate
32
beneath the emitter
30
. The n-tank
52
serves as a drain for the FET
50
and may be formed via conventional masking and ion implantation processes. The FET
50
also includes a source
54
and a gate electrode
56
. The gate electrode
56
is separated from the substrate
32
by a gate dielectric
57
and a field oxide layer
58
. The opening
40
in the high atomic mass layer
46
is typically about 10 microns in diameter, while the n-tank
52
is typically about 13 microns in diameter. The emitter
30
is typically about a micron wide, and several (e.g., four or five) emitters
30
are included together with each n-tank
52
, although only one emitter
30
is illustrated.
The substrate
32
may be formed from p-type silicon material having an acceptor concentration N
A
ca. 1-5×10
15
/cm
3
, while the n-tank
52
may have a surface donor concentration N
D
ca. 1-2×10
16
/cm
3
. A depletion region
60
is formed at a p-n junction between the n-tank
52
and the p-type substrate
32
.
In operation, the extraction grid
38
is biased to a voltage on the order of 100 volts, although higher or lower voltages may be used, while the substrate
32
is maintained at a negative voltage. Signals coupled to the gate
56
of the FET
50
turn the FET
50
on, allowing electrons to flow from the source
54
to the n-tank
52
and thus to the emitter
30
. Intense electrical fields between the emitter
30
and the extraction grid
38
then cause field emission of electrons from the emitter
30
. A larger positive voltage, ranging up to as much as 5,000 volts or more but often 2,500 volts or less, is applied to the faceplate
20
via the transparent conductive layer
24
. The electrons emitted from the emitter
30
are accelerated to the faceplate
20
by this voltage and strike the cathodoluminescent layer
26
. This causes light emission in selected areas, i.e., those areas adjacent to where the FETs
50
are conducting, and forms luminous images such as text, pictures and the like. Integrating the FETs
50
in the substrate
32
to provide an active display
10
(i.e., a display
10
including active circuitry for addressing and providing control signals to specific emitters
30
etc.) yields advantages in size, simplicity and ease of interconnection of the display
10
to other electronic componentry.
Visible photons from the cathodoluminescent layer
26
and photons that travel through the faceplate
20
can also travel back through the openings
40
. When photons travel through the portions of the extraction grid
38
exposed by the openings
40
and impinge on the substrate
32
, electron-hole pairs are generated. When electron-hole pairs are produced near the p-n junction between the n-tank
52
and the p-type substrate
32
, the electrons and holes are efficiently separated by the electrical fields associated with the p-n junction. The electrons are swept into the n-tank
52
and the holes are swept into the p-type substrate
32
surrounding the n-tank
52
. The electrons provide an undesirable component to electrons emitted by the emitter
30
. This results in distortion in the images produced by the display
10
.
For example, a blue pixel emitting blue light could provide a photon that reaches semiconductor material underlying the emitter
30
associated with an adjacent red pixel, which is not intended to be emitting light. This may cause an emitter current component resulting in an anode current in the red pixel, thus providing unwanted red light and thereby distorting the color intended to be displayed.
Alternatively, an area intended to be a dark area in the display
10
may emit light when that area is exposed to high ambient light conditions. These effects are undesirable and tend to reduce display dynamic range in addition to distorting the intended image.
There is therefore a need for a way to shield p-n junctions associated with monolithic emitters for use in field emission displays from photons incident on exposed portions of the extraction grid.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, a field emission display includes a substrate, a plurality of emitters formed on the substrate, a semiconductor device formed in or on the substrate for controlling the flow of electrons to the emitters, and a dielectric layer formed on the substrate. The dielectric layer includes an opening formed about each of the emitters. The display also includes an extraction grid formed substantially in a plane of tips of the plurality of emitters and includes openings each formed about and in close proximity to a tip of one of the plurality of emitters. Significantly, the extraction grid is fabricated from germanium.
As a result, the extraction grid has significantly greater optical absorption of light incident on it through openings in the layers on it. This prevents visible photons from traveling through the extraction grid and creating electron-hole pairs in a depletion region associated with the semiconductor device. This reduces distortion in field emission displays.
REFERENCES:
patent: 4422732 (1983-12-01), Ditzik
patent: 5151061 (1992-09-01), Sandhu
patent: 5186670 (1993-02-01), Doan et al.
patent: 5210472 (1993-05-01), Casper et al.
patent: 5212426 (1993-05-01), Kane
patent: 5319279 (1994-06-01), Wata
Moradi Behnam
Zhang Tianhong
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Ramsey Kenneth J.
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