Extracting high frequency impedance in a circuit design...

Details Extracting high frequency impedance in a circuit design... Extracting high frequency impedance in a circuit design...

2007-02-08

2008-11-18

Barlow, Jr., John E. (Department: 2863)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Electrical signal parameter measurement system

C702S155000, C257S728000, C257S738000, C257S784000, C340S870020, C324S207150, C324S654000, C324S763010

Reexamination Certificate

active

07454300

ABSTRACT:
Exemplary impedance extraction methods, systems, and apparatus are described herein. In one exemplary embodiment, at least a portion of a circuit description indicative of a circuit layout is loaded. A signal-wire segment is selected. Loop inductance values and loop resistance values for the signal-wire segment are determined at at least a first frequency of operation and a second frequency of operation. Values for one or more inductance components and one or more resistance components of a broadband representation of the signal-wire segment are computed and stored. In this embodiment, the broadband representation comprises at least one but no more than two parallel-coupled resistance components and inductance components. Computer-readable media storing computer-executable instructions for causing a computer to perform any of the disclosed methods or storing data or information created or modified using any of the disclosed techniques are also disclosed.

REFERENCES:
patent: 7013442 (2006-03-01), Suaya et al.
patent: 7319946 (2008-01-01), Bowen et al.
patent: 2003/0131334 (2003-07-01), Suaya et al.
patent: 2004/0078176 (2004-04-01), Bowen et al.
patent: 2005/0120316 (2005-06-01), Suaya et al.
patent: 2006/0031055 (2006-02-01), Sheehan
patent: 2006/0143586 (2006-06-01), Suaya et al.
patent: 2006/0282492 (2006-12-01), Suaya et al.
patent: 2007/0225925 (2007-09-01), Suaya et al.
patent: 2007/0226659 (2007-09-01), Suaya et al.
patent: 2008/0072189 (2008-03-01), Bowen et al.
Ranjan et al. “Use of Symbolic Performance Models in Layout-Inclusive RF Low Noise Amplifier Synthesis,” Sep. 2004, IEEE, 130-134.
“ASITIC: Analysis and Simulation of Spiral Inductors and Transformers for ICs,” downloaded from http://rfic.eecs.berkeley.edu/˜niknejad/asitic.html, 1 p. (document not dated, downloaded on Aug. 15, 2006).
Beatson et al., “A short course on fast multipurpose methods,” inWavelets, Multilevel Methods and Elliptic PDEs, 37 pp. (1997).
Beattie et al., “Efficient Inductance Extraction via Windowing,”Proc. Design, Automation, and Test in Europe, pp. 430-436 (2001).
Beattie et al., “Hierarchical Interconnect Circuit Models,” 7 pp. (also published as Beattie et al., “Hierarchical Interconnect Circuit Models,”Proc. ICCAS, pp. 215-221 (Nov. 200)).
Brassil et al., “The Manhattan Street Network: a high performance, highly reliable metropolitan area network,”Computer Network ISDN System, vol. 26, No. 6-8, pp. 841-858 (1994).
Cadence Design Systems, Inc., “Assura Parasitic Extraction,” 5 pp., downloaded from http://www.cadence.com. (2004).
Cadence Design Systems, Inc., “Assura Parasitic Extraction 3.1.3 Options,” 5 pp., downloaded from http://www.cadence.com (2005).
Chen et al., “Inductwise: Inductance-Wise Interconnect Simulator and Extractor,”IEEE Trans. CAD of IC and Systems, vol. 22, No. 7, pp. 884-894 (2003).
Dennis, Jr. et al.,Numerical Methods for Unconstrained Optimization and Nonlinear Equations, pp. xi, 68-84 (1996).
Deutsch et al., “When are Transmission-Line Effects Important for On-Chip Interconnections?, ”IEEE Trans. on Microwave Theory and Techniques, vol. 45, No. 10, pp. 1836-1846 (Oct. 1997).
Devgan et al., “How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit ElementK, ”IEEE, pp. 150-155 (2000).
Escovar et al., “An Improved Long Distance Treatment for Mutual Inductance,”IEEE Trans. Computer-Aided Design, vol. 24, No. 5, pp. 783-793 (May 2005).
Escovar et al., “Mutual Inductance Extraction and the Dipole Approximation,”ACM, pp. 162-169 (2004).
Escovar et al., “Optimal Design of Clock Trees for Multigigahertz Applications,”IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, No. 3, pp. 329-345 (Mar. 2004).
Escovar et al., “Transmission line design of Clock Trees,”IEEE, pp. 334-340 (2002).
Greenhouse, “Design of Planar Rectangular Microelectronics Inductors,”IEEE Trans. on Parts, Hybrids and Packaging, vol. 10, No. 2, pp. 101-109 (Jun. 1974).
Grover,Inductance Calculations Working Formula and Tables, pp. 1, 31-61 (1946).
Gupta et al., “The Elmore Delay as a Bond for RC Trees with Generalized Input Signals,”IEEE Trans. on Computer-Aided Design, vol. 16, No. 1, pp. 95-104 (1997).
Harrington,Field Computation by Moment Methods, pp. 1-211 (1993).
He et al., “SPIE: Sparse Partial Inductance Extraction,” 4 pp. (also published as He et al., “SPIE: Sparse Partial Inductance Extraction,”Design Automation Conference, pp. 137-140 (1997)).
Higham, “Factorizing Complex Symmetric Matrices with Positive Definite Real and Imaginary Parts,”Mathematics of Computation, vol. 67, No. 224, pp. 1591-1599 (Oct. 1998).
Hu et al., “Efficient PEEC-based Inductance Extraction using Circuit-Aware Techniques,”IEEE, 6 pp. (2002).
Ismail et al., “Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits,”IEEE Trans. on VLSI Systems, vol. 8, No. 2, pp. 195-206 (Apr. 2000).
Ji et al., “KSim: A Stable and EfficientRKCSimulator for Capturing On-Chip Inductance Effect,”IEEE, pp. 379-384 (2001).
Ji et al., “Spice Compatible Circuit Models for Partial Reluctance K,”IEEE, pp. 787-792 (2004).
Kamon et al., “Fasthenry: A Multipole-Accelerated 3-D Inductance Extraction Program,”IEEE TRans. Microwave Theory Tech., vol. 42, No. 9, pp. 1750-1758 (Sep. 1994).
Krauter et al., “Generating Sparse Partial Inductance Matrices with Guaranteed Stability,”IEEE, pp. 45-52 (1995).
Krauter et al., “Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis,”ACM, pp. 303-308 (1998).
Nabors et al., “FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program,”IEEE Trans. on Computer-Aided Design, vol. 10, No. 11, pp. 1447-1459 (Nov. 1991).
Niknejad et al.,Design, Simulation and Applications of Inductors and Transformers for SI RF ICs, pp. 64-69 (2000).
Paul,Analysis of Multiconductor Transmission Lines, pp. 46-63 (1994).
Ruehli, “Inductance CAlculations in a Complex Integrated Circuit Environment,”IBM J. Res. Develop., pp. 470-481 (1972).
Sakurai, “Closed-Form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSI's,”IEEE Trans. on Electron Devices, vol. 40, No. 1, pp. 118-124 (Jan. 1993).
Sequence Design, Inc., “Columbus,” 2 pp. (2005).
Shepard et al., “Full-chip, three-dimensional, shapes-based RLC extraction,” 8 pp. (also published as Shepard et al., “Full-chip, three-dimensional, shapes-based RLC extraction,”IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, No. 5, pp. 711-727 (May 2004)).
Synopsys Inc., “HSpice The Gold Standard for Accurate Circuit Simulation,” 4 pp. (2006).
Zhong et al., “Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects,”IEEE, pp. 428-433 (2002).

Affiliated with

Also associated with

Rating

Extracting high frequency impedance in a circuit design... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Extracting high frequency impedance in a circuit design..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Extracting high frequency impedance in a circuit design... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4031630