Extracting accurate and efficient timing models of latch-based d

Details Extracting accurate and efficient timing models of latch-based d Extracting accurate and efficient timing models of latch-based d

1996-11-15

2000-02-08

Teska, Kevin J.

39550006, 3955004, G06F 1750

Patent

active

060235683

ABSTRACT:
A method and an apparatus for constructing a model of a digital circuit which contains level sensitive latches. The model allows for time borrowing amongst latches. Chains of latches or latch paths are collapsed together. The resulting model can be used for simulation or synthesis.

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