Externally controlled DSP with input/output FIFOs operating asyn

Details Externally controlled DSP with input/output FIFOs operating asyn Externally controlled DSP with input/output FIFOs operating asyn

1995-06-06

1997-08-05

Lall, Parshotam S.

G06F 1300

Patent

active

056550901

ABSTRACT:
A means of making a digital signal processing function perform independently of the system processor and appear as a hardware FIFO. The architecture of the present invention comprises a digital signal processing means connected between the data output of a first FIFO buffer and the data input of a second FIFO buffer, a control means for controlling the digital signal processing means as a function of the presence and absence of data in the first FIFO buffer and said second FIFO buffer and control signals received from a source of control signals. Data throughput is performed asynchronously and independently of the system environment and comprises the following steps: receiving data on the data input of the first FIFO buffer, transferring that data to the digital signal processor, processing the data, then transferring the processed data to the second FIFO buffer to be output when the data receiver is ready to accept to data.

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