External write pulse control method and structure

Details External write pulse control method and structure External write pulse control method and structure

1996-12-21

1998-06-09

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365195, 365201, G11C 700

Patent

active

057645922

ABSTRACT:
A method and control circuit structure for externally controlling the width of a write pulse of a synchronous integrated circuit memory device is disclosed. The method and control circuit provide for a test mode in which the width of the write pulse of the synchronous integrated circuit memory device may be externally controlled to be entered. After entering the test mode, the start of a write pulse of the synchronous integrated circuit memory device is triggered by a transition of a clock signal from a first logic state to a second logic state. The termination of the write pulse is accomplished by selective manipulation of an external control signal external to the synchronous integrated circuit memory device.

REFERENCES:
patent: 4947374 (1990-08-01), Wada et al.
patent: 4962487 (1990-10-01), Suzuki

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