External procedure invocation apparatus utilizing internal branc

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395375, 36423221, 3642421, 36424342, 36424341, 364243, 3642613, 3642624, 3642632, 364DIG1, G06F 1314, G06F 900

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052875229

ABSTRACT:
A system includes first and second processing units which are interconnected by a bidirectional bus. The first processing unit is a microprocessor chip programmed for executing procedures stored in an on-chip instruction cache unit. The second processing unit receives requests from an external source such as a system bus. The microprocessor chip includes a branch vector facility which connects to the bus. The second processing unit in response to an external request, generates a vector branch address. The processing unit transfers the vector branch address to the branch vector facility for storage along with setting a write indicator. The microprocessor chip, upon detecting that the write indicator was set, branches to the procedure specified by the branch vector address for executing the instructions of the procedure to carry out those operations required for processing the external request or event.

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