Patent
1995-12-15
1998-06-16
Lee, Thomas C.
395878, 395557, 395835, G06F 1502, G06F 1314
Patent
active
057686270
ABSTRACT:
The timing of control signals in a parallel port is measured and adjusted to achieve optimum timing of these control signals. At boot-up, a routine writes alternating data to the control register of the parallel port. The control register drives control signal over a parallel-port cable to an external parallel-port device connected to the parallel port of a personal computer (PC). Transitions of the control signal trigger an external timer in the external parallel-port device which measures the pulse width of the control signal. The measured pulse width is sent back to the PC over the parallel cable and compared to a target pulse width. When the measured pulse width is less than the target, additional intervening instructions are inserted between writes to the parallel-port control register. The intervening instructions are a simple delay loop. Alternately the internal timer on the PC may be used. Since the accuracy is less for the internal timer, many IO writes are performed to average out errors. Several external devices having cross-over adapters may be coupled together and addressed separately. Two of the ground signals in the parallel port are used as addressing grounds.
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Jones Larry
Mambakkam Sreenath
Venkidu Arockiyaswamy
Auvinen Stuart T.
Lee Thomas C.
On Spec Electronic, Inc.
Perveen Rehana
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