External memory access control for a processing system

Details External memory access control for a processing system External memory access control for a processing system

1992-07-21

1995-04-18

Richardson, Robert L.

Boots, shoes, and leggings

395750, 3642703, 3642706, 3642715, 364DIG1, G06F 1300

Patent

active

054086396

ABSTRACT:
A processing system of the type having a processor which accesses external memory for data and/or instructions which includes an improved external memory access control system for rendering the external memory enable time durations independent from the number of external memory accesses per unit of time for reducing power consumption of the processing system. The control system includes a selectably programmable clock for providing a clock signal of one of at least two speeds for determining the external memory access rate. The control system also includes enable duration control structure coupled to the selectably programmable clock. The enable duration control structure is arranged to enable the external memory for time durations during each memory access which are independent from the external memory access rate. Further, the enable duration control structure includes substructure for changing the duty cycle of external memory enable time duration control signals based upon the selected clock speed.

REFERENCES:
patent: 4893271 (1990-01-01), Davis et al.
patent: 5155480 (1992-10-01), Niijima
IBM Technical Disclosure Bulletin, "Memory Controller Which Automatically Adjusts To Changes In System Clock Rate", vol. 32, No. 8A, pp. 265-266, Jan. 1990.
IBM Technical Disclosure Bulletin, "Programmable Memory Controller", vol. 31, No.9, pp. 351-353, Feb. 1989.

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