Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-02-28
2004-08-31
Greene, Pershelle L. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S751000, C257S744000, C257S764000, C257S766000, C257S767000, C257S772000, C257S701000, C257S738000, C257S741000, C257S750000
Reexamination Certificate
active
06784543
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an external connection terminal and a semiconductor device and, more particularly, an external connection terminal used in the semiconductor device, the electronic parts, the wiring substrate, the package, etc. and a semiconductor device having projection-like connection terminals.
2. Description of the Prior Art
The solder is employed to connect electrically and mechanically the semiconductor device to the ceramic substrate or to connect electrically and mechanically the electronic parts to the wiring substrate.
For example, the solder is formed on the metal wiring like the ball, or is coated on the metal wiring by the screen printing, and then is jointed to the metal wiring by the heating/melting. Normally the metal wiring is formed of the metal containing a large amount of aluminum (Al) or copper (Cu).
When the solder is jointed to the surface of the metal wiring, normally the nickel (Ni) layer is formed as the diffusion barrier metal (barrier metal) layer between the solder and the metal wiring, for the purpose of preventing the mutual diffusion the constituent element of the metal wiring and the tin (Sn) in the solder. As the method of forming the nickel layer, the employment of the electroless plating method without the feeding terminal is advantageous to shorten the film forming steps and to suppress the cost. Also, in order to improve the wettability of the solder, sometimes the gold layer is formed on the nickel layer.
The state before the solder is jointed to the metal wiring on which the nickel layer and the gold; layer are formed is shown in
FIG. 1
, for example. In
FIG. 1
, the nickel (Ni) layer
103
and the gold (Au) layer
104
are formed on a part of the surface of the metal wiring
102
on the insulating film
101
by the electroless plating method, and the tin alloy solder
105
is placed thereon.
Also, it is set forth in Patent Application Publication (KOKAI) 2000-133739 to form another solder layer made of the material, that has the melting point higher than the tin alloy solder and contains an amount of tin smaller than the tin alloy solder, on the gold layer
104
by the electroless plating method, etc. before the formation of the tin alloy solder
105
.
As another structure of the solder layer and the metal wiring, it is set forth in Patent Application Publication (KOKAI) 2000-22027 to form the nickel plating layer, the palladium plating layer, and the gold plating layer in order on the wiring.
Also, sometimes the gold film is employed in place of the tin alloy solder layer. As the barrier metal film between the gold film and the wiring, it is set forth in Patent Application Publication (KOKAI) Hei 3-209725, for example, to form the nickel film by the electroless plating method.
In addition, as the layer structure of the wiring and the solder layer, various structures have been known.
For example, in Patent Application Publication (KOKAI) Hei 9-8438, it is set forth to form the electroless nickel plating film, the substitutional palladium film, the electroless palladium plating film, the substitutional gold plating film, and the electroless gold plating film in sequence on the surface of the wire bonding terminal.
In Patent Application Publication (KOKAI) Hei 5-299534, the structure in which the first layer made of the electroless nickel plating film, the second layer made of the electroless nickel-boron plating film or the electroless nickel-phosphorus plating film, and the third layer made of the palladium film or the palladium alloy film are formed in sequence on the metal outer ring is set forth as the stem to be soldered. Here the palladium film or the palladium alloy film is formed to improve the wettability of the solder.
Meanwhile, the conductive pins used as the external connection terminals of the semiconductor device are set forth in Patent Application Publication (KOHYO) Hei 9-505439, for example. The surface of the semiconductor device on the conductive pin forming side is covered with the plastic package. Also, the projection electrodes used as the external connection terminals of the semiconductor device are set forth in Patent Application Publication (KOKAI) Hei 5-55278, for example. A real chip size of the semiconductor device on which the conductive pins and the projection electrodes are formed can be achieved.
As described above, the nickel film or the nickel alloy film is formed on the surface of the wiring, the pin, or the stem to which the solder is jointed, and then the layer having a single layer structure or the multi-layered structure made of gold, palladium, or the like is formed thereon.
However, according to such structure, after the solder is jointed to the wiring, the pin, or the stem by the heating/ melting, such solder is easily peeled off from the wiring, the pin, or the stem by the external impact, etc.
In Patent Application Publication (KOKAI) 2000-133739, it is set forth that, as the cause of such peeling-off, the concentration of the phosphorus contained in the nickel layer, that is formed by the electroless plating, is increased at the time of melting the solder.
By the way, in the external connection terminals formed on the package of the semiconductor device or on the semiconductor device, there are following respects to be improved.
For example, as set forth in Patent Application Publication (KOKAI) Hei 5-55278 and Patent Application Publication (KOHYO) Hei 9-505439, in the semiconductor device which is miniaturized to the same size as the chip, the capability of relaxing the thermal stress is lowered rather than the package in the prior art and thus the stress tends to concentrate to the external connection terminal packaging portion.
In the semiconductor device set forth in Patent Application Publication (KOKAI) Hei 5-55278, the plastic sealing is formed only on one surface of the silicon chip, and side surfaces and the back surface of the silicon chip are exposed. Since the silicon has the easily fragile property, there is the possibility that, if the silicon chip is thinned more and more, the circuits formed in the chip are damaged by the silicon chipped off from the exposed surface side.
That is, in the package which is miniaturized to the same size as the chip, there is the possibility that the chipping or the crack on the back surface or the side surfaces causes the damage of the circuits and thus yield of the fabrication is lowered.
The structure set forth in Patent Application Publication (KOHYO) Hei 9-5065439 aims at the improvement of the packaging reliability by forming the electrode on the metal pad by using the deformable metal wire. This electrode can be formed by the normal wire bonder method, but the formation tact needs the time that is several times the normal bonding and also needs much production cost. Also, the electrode made of the metal wiring is covered with the metal shell formed by the electrolytic plating method. In this case, if the electrolytic plating is applied in the situation that the wiring patterns connected to the metal wiring are exposed, the distribution of the film thickness of the metal shell is largely affected by the distribution of the current density in the electrolytic plating. Thus, since it is hard to get the sufficient and uniform thickness, it is difficult to achieve the fine pitch of the electrode made of the metal wire. In addition, if the metal shell is formed by the electrolytic plating method and then the wirings are formed by etching the metal film, the migration of the wiring material is concerned about.
Also in Patent Application Publication (KOHYO) Hei 9-505439, it is set forth that pin-like metal wires are covered with the nickel layer and the gold layer and then the metal wires are connected to the external devices by the solder. In this case, if the nickel layer is formed by the electroless plating method, there is such a possibility that the crack is caused between the solder and the metal wire, as described above.
SUMMARY OF THE INVENTION
It is an object of the
Aiba Yoshitaka
Fujisawa Tetsuya
Ikumo Masamitsu
Makino Yutaka
Matsuki Hirohisa
Armstrong Kratz Quintos Hanson & Brooks, LLP
Fujitsu Limited
Greene Pershelle L.
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