External asynchronous input tester for bit slice machines

Details External asynchronous input tester for bit slice machines External asynchronous input tester for bit slice machines

1987-07-01

1990-05-15

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

375110, 328 63, H04L 700

Patent

active

049264451

ABSTRACT:
A timing circuit is disclosed for use with microprocessors which perform bit slicing within their arithmetic logic units. This timing circuit combines the synchronization of digital data inputs with the generation of the clocking signal, by dividing an oscillator frequency signal into the clocking signal, using a number of cycles of the oscillator frequency signal to synchronize the digital data inputs with the clocking signal, and outputting a synchronized clocking signal as soon as the digital data input signals are synchronized with the clocking signals. In a situation where the clock is derived by dividing the oscillator frequency by four, two of the four oscillator cycles are used to resynchronize the test input. The waste of overhead wait states and individual input resynchronization circuits are eliminated.

REFERENCES:
patent: 3343141 (1967-09-01), Hackl
patent: 4241416 (1980-12-01), Tarczy-Hornoch
patent: 4253183 (1981-02-01), Taylor et al.
patent: 4381540 (1983-04-01), Lewis et al.
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patent: 4454589 (1984-06-01), Miller
patent: 4528641 (1985-07-01), Burrows
patent: 4677433 (1987-06-01), Catlin et al.
patent: 4754456 (1988-06-01), Yato et al.

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