Extension of accuracy of a flash ADC by 1-bit through...

Details Extension of accuracy of a flash ADC by 1-bit through... Extension of accuracy of a flash ADC by 1-bit through...

2006-10-26

2008-05-27

Jeanglaude, Jean B (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S156000

Reexamination Certificate

active

07379010

ABSTRACT:
ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an intepolating comparator. The intepolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.

REFERENCES:
patent: 5748132 (1998-05-01), Matsuzawa
patent: 6002800 (1999-12-01), Donelly et al.
patent: 6107949 (2000-08-01), Gross, Jr.
patent: 6720901 (2004-04-01), Nakamoto

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