Extensible memory architecture and communication protocol...

Details Extensible memory architecture and communication protocol... Extensible memory architecture and communication protocol...

2005-05-31

2009-12-29

Shah, Kamini S (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Emulation

C703S013000, C703S024000, C703S028000, C711S122000, C712S002000, C712S010000, C712S020000, C712S022000, C712S039000, C714S028000, C714S735000, C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07640155

ABSTRACT:
A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. Being coupled via a serial link, the reconfigurable logic devices each have an input connection for receiving incoming data packets and an output connection for providing outgoing data packets. The serial link couples the input and output connections of successive reconfigurable logic devices to form a dataring structure for distributing the data packets among the reconfigurable logic devices. Thereby, the dataring structure maintains data synchronization among the reconfigurable logic devices such that the distribution of the target interface logic among the reconfigurable logic devices is transparent to software.

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