Extending non-volatile memory endurance using data encoding

Details Extending non-volatile memory endurance using data encoding Extending non-volatile memory endurance using data encoding

2003-02-18

2004-09-21

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

C714S718000, C365S185290

Reexamination Certificate

active

06794997

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the field of computer systems, and more particularly to microcontroller based embedded systems incorporating non-volatile memories.
BACKGROUND OF THE INVENTION
Embedded systems are systems designed to perform a dedicated function and are often part of a larger system or product. An embedded system may incorporate microprocessors or microcontrollers along with memory and special purpose peripherals, including timers, counters, A/D converters and I/O interface circuitry. The memory included in an embedded system will typically include program memory and data memory. Data memory is usually based on static or dynamic RAM and is volatile, i.e. it will not retain its contents after power is removed. Often the program memory is stored in a non-volatile technology, such as a mask programmed ROM or flash EEPROM, and doesn't change over the lifetime of the product. There is frequently a need for another type of memory, a non-volatile memory that can be dynamically written, to be used, for example, to store configuration or logging information. This memory is usually a relatively small amount of memory, and since it is non-volatile it will retain its contents after power is removed from the system, so that the next time power is applied, the previous contents can be read. In some cases dynamically writable non-volatile memories are incorporated on-chip in single chip microcontrollers. For example, the PIC12F629 manufactured by Microchip Technology incorporates 128 bytes of EEPROM data memory that can be re-programmed during normal operation.
Non-volatile memory cells are commonly constructed using a floating gate technology, although other technologies are possible. In a floating gate memory cell, charge is deposited or removed from a floating gate to either program or erase the cell. Since the gate is surrounded by oxide, it will retain its charge almost indefinitely. However, the process of erasing and programming a floating gate memory cell introduces stress to the surrounding oxide and thus wears down the cell. For this reason, devices incorporating floating gate memory cells are generally rated with an endurance limit, usually expressed in terms of the number of erase/program cycles that a memory cell, or group of memory cells, can go through. A typical number of cycles specified by a manufacturer is in the range of 10,000 cycles to 1,000,000 cycles, depending on the particular device, and sometimes the environmental conditions, such as ambient temperature. For example the EEPROM array of the PIC12F629 is rated at 10,000 cycles minimum and 100,000 cycles typical at an ambient temperature range of +85° C. to +125° C. and 100,000 cycles minimum and 1,000,000 cycles typical at an ambient temperature range of −40° C. to +85° C.
In some circumstances it is desirable to cycle non-volatile memories more times over the lifetime of a product than the limit imposed by floating gate memory cell technology. One way to get around these limitations is to use battery backed-up static RAM (SRAM) instead of floating gate based EEPROM. This technique includes a battery in addition to conventional volatile memory. When system power is removed, the battery takes over and supplies power to the SRAM memory cells, allowing them to retain their contents until system power is once again supplied. An example of a self-contained non-volatile memory device based on this design is the M48Z02 manufactured by ST Microelectronics. This device incorporates 2048 bytes of volatile memory, voltage sense and switching circuitry and a lithium battery into a single package. While these types of devices have no erase/write cycle limitations, they are expensive, have a large footprint and cannot be incorporated on-chip into other devices.
Another method of addressing endurance limitations of non-volatile memory is to include both volatile memory and non-volatile memory as a single unit. When power is applied, the contents of the non-volatile memory are read into the contents of the volatile memory. During normal operation, reads and writes take place to the volatile memory. Before power is removed, the contents of the volatile memory are written back to the non-volatile memory. The writing of the non-volatile memory can occur at specific times, at pre-programmed intervals or under the control of shutdown circuitry. This type of system utilizes the volatile memory to buffer write operations, such that a smaller number of writes takes place to the non-volatile memory. An example of a product based on this design is the CAT22C10 manufactured by Catalyst Semiconductor, Inc. This device incorporates a 256-bit EEPROM array, a 256-bit static RAM (SRAM) array, a control signal (/RECALL) that cause the contents of the EEPROM to be transferred into the SRAM, and a control signal (/STORE) that causes the contents of the SRAM to be written into the EEPROM. The CAT22C10 is rated at up to 100,000 store operations due to the endurance limitations of the EEPROM array, but can perform unlimited recall operations and can perform unlimited writes to the SRAM. While this type of design can reduce the number of erase/program cycles, it is expensive since twice the number of memory cells are required. Furthermore, this type of design suffers from the problem that the EEPROM array and the SRAM array are not always consistent. Unless it can be Guaranteed that the store operation will always take place before power is removed, there is a chance that a data write will be lost. The alternative of forcing every write to the SRAM generate a store operation eliminates the endurance advantage of having the SRAM.
It is therefore desirable to allow data to be written to non-volatile memory more times than is allowed by the erase/program cycle limit specified by the manufacturer. An inexpensive and small design is preferred that does not utilize batteries or duplicate arrays of volatile memories. Additionally, it is desirable to allow off the shelf microcontrollers to be used without hardware modifications. Finally it is preferred to allow data to continue to be stored and retrieved from non-volatile memory in the presence of failures of the underling memory cells.
SUMMARY OF THE INVENTION
The present invention is a method and apparatus for increasing the endurance of a non-volatile memory. A read operation is performed by converting a stored bit pattern into a data value where the data value has a smaller number of bits than the stored bit pattern. A write operation is similarly performed by converting a data value into a stored bit pattern where the data value has a smaller number of bits than the stored bit pattern. Additionally, the writing of information utilizes the previously stored bit pattern such that only a subset of the bits in the newly stored bit pattern are changed from their previously stored values. This subset may be empty if no bits need to be changed from their previous states.
In one embodiment of the invention, the read conversion includes reading two bit patterns from memory and comparing them for equality. In this embodiment, the write conversion includes leaving the memory unchanged, changing one bit pattern to be equal to a second bit pattern, or by changing the second bit pattern to be equal to the first bit pattern.
In another embodiment of the invention, the read conversion includes using a gray code to binary conversion. In this embodiment, the write operation includes either leaving the memory unchanged or utilizing a gray code to binary conversion, followed by a two's complement add, followed by a binary to gray code conversion.
Information can be stored such that a bit pattern is striped across multiple words such that one bit is stored in each word. It is also possible to accommodate one or more bit failures by repeating the write operation using a different store bit pattern such that the new bit pattern will be decoded into the same data value.

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