Amplifiers – With amplifier condition indicating or testing means
Reexamination Certificate
2000-01-12
2001-10-23
Lee, Benny (Department: 2817)
Amplifiers
With amplifier condition indicating or testing means
C330S129000
Reexamination Certificate
active
06307429
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to power amplifier control circuits, and in particular, to power ramp up and ramp down control circuits for power amplifiers.
2. Description of the Related Art
Power amplifiers for amplifying radio frequency (RF) signals for wireless transmission are used in many applications. One increasingly common application is that of a radio telephone communication system, such as a cellular telephone system. One example of such a system is a time division multiple access (TDMA) communication system, such as that based upon the Global System for Mobile Communication (GSM) standard. In such a system, relatively narrow single channels within the prescribed RF spectrum are shared by multiple telephones, with each one being allocated a specific time slot on a repetitive basis. During its assigned time slot, the transceiver must set its outgoing signal to the appropriate frequency and ramp up the power level of such signal by ramping up the power amplification of the power amplifier to the appropriate level. Once the data has been transmitted, the power amplification of the power amplifier must then be ramped down prior to the beginning of the next time slot so as to not cause interference with the user assigned to that time slot.
This ramping up and down of the power amplification provided by the power amplifier defines a power profile which must be maintained in accordance with strict specifications. If such power ramping is not accurately controlled then spurious and other undesired signals may be generated in adjacent time slots or at improper frequencies, thereby causing interference with other users within the system, as well as possibly causing interference with other users of other systems elsewhere within the RF spectrum.
The conventional technique to maintain this control over the power amplifier uses a feedback loop with a reference power ramp curve that is generated in accordance with a programmable power profile data table which drives a digital-to-analog converter (DAC). Generally the ramp generator circuit is implemented in an integrated circuit (IC) and the power control loop itself is implemented using components external to such IC. (Examples of this approach can be found in the disclosures of U.S. Pat. Nos. 5,150,075 and 5,748,037, the disclosures of which are incorporated herein by reference.) Typically some form of processor, such as a microprocessor or digital signal processor, is used to generate the ramp and exercise control over the feedback loop for the power ramp control circuit.
While such systems perform reasonably well, they nonetheless suffer from a number of disadvantages. For example, due to the use of external components for the power control loop itself, it is difficult, if not impossible, to control the dynamic range of the loop. Plus, the use of external components is generally significantly more expensive than if the power control loop were more fully integrated with the ramp generator circuit. Furthermore, any control over the power control loop itself would require additional control tasks to be performed by the microprocessor or DSP. Accordingly, it would be desirable to have a power amplifier control loop which can be subjected to greater levels of control without requiring additional processor resources.
SUMMARY OF THE INVENTION
An extended power ramp table for a power amplifier control loop in a TDMA communication system in accordance with the present invention provides for the storage and use of additional programmable control data for use in conjunction with the power ramp profile data provided by the power ramp table. These additional control data can be used to control the dynamic range of the power amplifier control loop during the turn-on and turn-off sequences with accurate timing and without requiring additional processor resources. For example, a control signal could be provided which forces the power amplifier to its final power value by changing the control loop to a feed forward configuration when transmitting at the maximum power level, thereby increasing the efficiency of the power amplifier. Another control signal can be used to increase the loop gain when small feedback signals from the power amplifier are being received or during the initial portion of the ramp up interval for closing the loop more quickly prior to the power ramp achieving its final value. Many other types of control can be exercised as desired by making these additional control signals programmable by the user.
In accordance with one embodiment of the present invention, an extended power ramp table for a power amplifier control loop in a time division multiple access (TDMA) communication system includes a power profile data table and a control data table. The power profile data table is configured to store power profile data and receive a clock signal and in accordance therewith read out the power profile data as a sequential series of discrete power data sets corresponding to discrete time segments of a defined power profile including turn-on and turn-off power profiles of a signal power amplifier. The control data table is configured to store control data and receive the clock signal and in accordance therewith read out the control data as a sequential series of discrete control data sets, wherein respective ones of the sequential series of discrete control data sets correspond to respective ones of the sequential series of discrete power data sets.
In accordance with another embodiment of the present invention, a power ramp control circuit for a power amplifier control loop in a time division multiple access (TDMA) communication system includes a data storage circuit, a digital-to-analog conversion circuit and a control signal amplifier circuit. The data storage circuit is configured to store data and receive a clock signal and in accordance therewith read out the data as: a sequential series of discrete power data sets corresponding to discrete time segments of a defined power profile including turn-on and turn-off power profiles of a signal power amplifier; and a sequential series of discrete control data sets; wherein respective ones of the sequential series of discrete control data sets correspond to respective ones of the sequential series of discrete power data sets. The digital-to-analog conversion circuit, coupled to the data storage circuit, is configured to receive the sequential series of discrete power data sets and in accordance therewith provide an analog signal with a sequential series of corresponding analog signal values. The control signal amplifier circuit, coupled to the digital-to-analog conversion circuit and the data storage circuit, is configured to receive the analog signal and the sequential series of discrete control data sets and to couple to the signal power amplifier and receive a detected power signal corresponding to a power level of an output signal from the signal power amplifier and in accordance therewith provide a power level control signal for the signal power amplifier.
These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.
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Philips Semiconductors, “Data Sheet, PCF5075, Power Amplifier Controller for GSM and PCN Systems”, Feb. 27, 1997, pp. 1-27.
Choe Henry
Dalla Valle Mark A.
Lee Benny
National Semiconductor Corporation
Wildman Harrold Allen & Dixon
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