Extended PHY addressing

Details Extended PHY addressing Extended PHY addressing

1998-03-19

2001-08-14

Marcelo, Melvin (Department: 2732)

Multiplex communications

Channel assignment techniques

Using a separate control line or bus for access control

C370S469000, C370S475000

Reexamination Certificate

active

06275498

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
None
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH
Not Applicable
BACKGROUND OF THE INVENTION
The present invention relates to telecommunications devices and more particularly, to a method and apparatus to permit access to and control over a greater number of PHYS than may be directly addressed using the Media Independent Interface protocol for direct PHY addressing.
Telecommunications devices such as bridges, routers and switches typically have a plurality of ports for connecting the device to different networks or subnetworks. Each port usually has at least one media access controller (MAC) for controlling access to the media in accordance with a predetermined network protocol. The MAC associated with a network protocol, such as the ethernet or fast ethernet protocol, interface to the physical media via logic which is known in the art as a PHY. The PHYS performs a number of interface functions. In particular, in the ethernet environment, the PHY performs a parallel to serial conversion of data forwarded by the MAC to the PHY and performs
4
B to
5
B encoding of such data to assure DC balance on the media. Furthermore, the PHY generates tri-level encoding of data, such as the MLT3 levels employed with 100Base-T. The PHY also receives the serial data stream from the media and converts the received serial data stream to a parallel data stream which is forwarded to the MAC. During the serial to parallel decoding, the PHY performs necessary
5
b
to
4
b
decoding of the received serial data stream.
The PHYS are controlled via a bidirectional serial management control bus such as the Media Independent Interface (MII) Management Interface specified in the IEEE Std 802.3u-1995 published by the Institute of Electrical and Electronic Engineers, Inc., New York, N.Y 10017 (2nd printing, Corrected Edition, Approved by the IEEE Standards Board Jun. 14 1995), which specification is incorporated herein by reference. The MII Management Interface Protocol is also described in a data sheet describing a commercially available component which is employed to implement PHYS in ethernet ports. The component is identified as the LXT970 Fast Ethernet Transceiver and is available from Level One Communications of Sacramento, California and is described in a data sheet bearing a copyright date of 1997, titled LXT970 Fast Ethernet Transceiver Data Sheet, which data sheet is incorporated herein by reference.
The MII Management Interface comprises a control bus and a protocol which permits the forwarding of control messages and information to a specified PHY from a processor and further permits the processor to access information within registers of PHYS coupled to the control bus. Each PHY which is coupled to the management control bus is assigned a five bit address which is used to identify the PHY. As a consequence of the five bit address limitation within the MII Management Interface specification, it is only possible to directly address 32 PHYS over a single management control bus. The five bit address limitation within the management control bus protocol presents an undesirable limitation on the number of PHYS which may be addressed via a single processor.
Port setup, management and statistics gathering operations within a telecommunications devices are often performed by an application processor which comprises a high-speed microprocessor. The processor employed to perform such functions is also typically employed to manage the PHYS within the device and thus must manage the transmission and reception of information over the management control bus. Burdening the processor with software control of the MII Management Bus operations can limit the available bandwidth of the processor to service and manage port configuration and statistics gathering functions. It would therefore be desirable to be able to allow a processor to manage the MII management bus transfers without using an inordinate amount of processor bandwidth for this purpose.
BRIEF SUMMARY OF THE INVENTION
In accordance with the present invention, a method and apparatus are disclosed for extending the addressing capabilities of a serial bidirectional PHY control bus, such as an MII Management Control Bus. Extension of the addressing capabilities of the control bus permits a single control processor to address a greater number of PHY interfaces than is possible given a fixed number of address bits specified within the MII Interface Specification. More specifically, a control processor is coupled to a plurality of bidirectional serial management control buses via programmable array logic. The programmable array logic is employed to direct information and control messages from the control processor to the appropriate Management Control Bus and to permit information to be retrieved from a PHY coupled to one of the buses. Selection signals from the control processor are used to select one of the plurality of control buses as the operative management bus. Finite state machines within the programmable array logic generate signals to selectively enable and disable drivers and receivers for the respective Management Control Buses so as to permit data flow in the proper direction through the programmable array logic. By addressing PHYS over a plurality of management buses, a single control processor may control more PHYS then can be addressed with the limited number of address bits specified within the management bus protocol.
Additionally the control processor drives a selected serial management bus through a serial peripheral interface (SPI) provided in the processor. The control processor has a clock speed many times greater than the clock speed of the management bus. To avoid unduly burdening the control processor with the software overhead needed to manage communications over the control bus directly at a significantly lower clock speed than the speed at which the control processor operates, information to be transmitted over a management bus is loaded by the control processor into the serial peripheral interface within the control processor. The serial peripheral interface then manages the information exchange over the respective Management Control Bus without further processor intervention. In this manner, the serial peripheral interface may be efficiently configured by the control processor and the serial peripheral interface can manage the information exchange between the SPI and the PHY independent of the control processor. The control processor bandwidth is thereby made available to perform configuration, port management and statistics monitoring functions pertaining to network ports controlled by the processor.


REFERENCES:
patent: 5485456 (1996-01-01), Shtayer et al.
patent: 5889778 (1999-03-01), Huscroft et al.
patent: 5978853 (1999-11-01), Crayford et al.

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