Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1990-04-30
1992-07-21
Hudspeth, David
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307468, H03K 19177
Patent
active
051325705
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an extended logical scale structure of a programmable logical array, and more particularly to an extended logical scale structure of a programmable logic array which makes it possible to extend the scale of a logic circuit formed by a single logic array to a scale equivalent to the scale of a logic circuit formed by a plurality of logic arrays.
2. Description of the Related Art
A programmable logic array (hereinafter simply referred to as a PLA) is hardware for a logical calculation which can achieve a programmable logic circuit, and is a logic operation circuit which can present a desired logic circuit by a simple structure and which execute logic operation at high speeds.
FIG. 1 shows a basic structure of a PLA. For the sake of simplicity, FIG. 1 illustrates a PLA which achieves a logic operation circuit having two inputs (x.sub.1, x.sub.2) and two outputs (y.sub.1, y.sub.2). An input x.sub.1 is supplied to an input buffer 11.sub.1. A positive logic output x.sub.1 of the input buffer 11.sub.1 is output to an input line 1.sub.1, and a negative logic output x.sub.1 thereof is output to an input line 1.sub.2. Similarly, an input is supplied to an input buffer 11.sub.2. A positive logic output x.sub.2 of the input buffer 11.sub.2 is output to an input line 1.sub.3, and a negative logic output x.sub.2 thereof is output to an input line 1.sub.4.
Resistors 12.sub.1 and 12.sub.2 each having an end connected to ground are connected to input terminals of output buffers 13.sub.1 and 13.sub.2 through output lines O.sub.1 and O.sub.2, respectively. Product term lines a.sub.1 and a.sub.2 extend in the direction perpendicular to the input lines 1.sub.1 -1.sub.4 and the output lines O.sub.1 and O.sub.2. The product term lines a.sub.1 and a.sub.2 are supplied with a high-level voltage Vcc through resistors 14.sub.1 and 14.sub.2, respectively.
Intersecting points where the input lines 1.sub.1 -1.sub.4 and the output lines O.sub.1 and O.sub.2 intersect with the product term lines a.sub.1 and a.sub.2 are called PLA intersecting points 15. A wiring group of the input lines 1.sub.1 -1.sub.4 and the product term lines a.sub.1 and a.sub.2 is called an AND array 16. A wiring group of the output lines O.sub.1 and O.sub.2 and the product term lines a.sub.1 and a.sub.2 is called an OR array 17.
The inputs x.sub.1 and x.sub.2 are drawn through the output buffers 13.sub.1 and 13.sub.2 as the outputs y.sub.1 and y.sub.2, which are represented by a logic formula of a desired sum-of-products style by making related groups of the PLA intersecting points 15 closed or open.
Now, a case is considered where hatched intersecting points among the PLA intersecting points 15 shown in FIG. 1 are made closed (short-circuits). In this case, the product term line a.sub.1 is logic 1 when both the logic x.sub.1 of the input line 1.sub.1 and the logic x.sub.2 of the input line 1.sub.4 are logic 1. The product term line a.sub.2 is logic 1 when both the logic x.sub.1 of the input one 1.sub.2 and the logic x.sub.2 of the input line 1.sub.3 are logic 1. When the output line O.sub.1 is logic 1 when at least one of the product lines a.sub.1 and a.sub.2 is logic 1. When the output line O.sub.2 is logic 1 when the product term line a.sub.1 is logic 1. Therefore, the logical relationship between the outputs y.sub.1, y.sub.2 and the inputs x.sub.1, x.sub.2 are as follows:
In a similar manner to the above-mentioned manner, a desired logic circuit can be formed by making a decision on whether each of the PLA intersecting points 15 should be made closed or open.
Conventionally, each of the PLA intersecting points 15 shown in FIG. 1 is formed by use of a fuse 18 shown in FIG. 2. In this case, all the fuses 18 corresponding the PLA intersecting points 15 are short-circuits at the stage of production. When a user uses PLA, a current pulse is applied to some of the fuses 18 selected based on the contents of a program achieved by a desired logic circuit. Thereby, the unnecessary fuse
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Shutou Hideki
Suenaga Fumihiro
Takeno Minoru
Fujitsu Limited
Hudspeth David
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