Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2000-08-24
2003-10-07
Pan, Daniel H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S213000, C712S300000, C712S207000, C712S227000, C710S307000, C711S172000
Reexamination Certificate
active
06631459
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an extended instruction word folding apparatus. More particularly, present invention relates to an extended instruction word folding apparatus for processing extended instruction words when a microprocessor using a fixed length instruction perform a general instruction word.
2. Background Information
In general, a microprocessor reads a program comprised of a set of a plurality of instruction words stored in a memory, interpreters the read program by an instruction interpreter, and executes an operation corresponding to each instruction by an execution unit.
An instruction word is called a variable length instruction word according to the length of the instruction word, that is, if a magnitude of the number of bits in an instruction word is diverse. Meanwhile, if the magnitude of the number of bits in all instruction words is same, the instruction word is called a fixed length instruction word.
A conventional microprocessor is divided into a CISC (Complex Instruction Set Computer) and a RISC (Reduced Instruction Set Computer), in which the CISC uses a variable length instruction word and the RISC uses a fixed length instruction word.
A variable length instruction word system has a diverse length according to the instruction word and many a kind of instruction words. However, since the length of the instruction word is variable, an instruction interpreter interpreting the instruction word has a complex configuration and a low execution speed.
Meanwhile, a fixed length instruction word system uses fixed length instruction words all of which the lengths are constant, in which a configuration of an instruction word interpreter is simple and a high speed operation is possible, but the length of the instruction word is fixed to thereby restrict the range of an operand to be represented. That is, since the length of the operand is smaller than the magnitude of a register or the magnitude of the address range of a storage device, a constant value larger than the magnitude of an instruction word or the address of the storage device cannot be made up with a single instruction word.
An extended instruction word method is to solve the above problems of the conventional variable length instruction word system and the conventional fixed length instruction word system. The extended instruction word system is equipped with an extended data storage device while adopting fixed length instruction words where the lengths of all instruction words are constant, to thereby represent instruction words of all lengths.
FIG. 1
is an operational diagram for an extended instruction word system.
As shown in
FIG. 1
, two extended instruction words are used in order to represent a constant value larger than the magnitude of an instruction word, or the address of a storage device. In
FIG. 1
, an operational code OP of an instruction word read from the storage device is interpreted. Here, if the operational code OP is a general instruction word, the instruction word is executed by an execution unit according to a corresponding operational code. Meanwhile, the operational code OP of the read instruction word is an extended instruction word, a first operand OPER
1
of the instruction word is stored in an extended data storage unit ER. In this case, if the extended instruction word is an extended instruction word which is firstly used following a general instruction word using extended data stored in the extended data storage unit ER, the higher upper bits than the first operand OPER
1
of the extended instruction word in the extended data storage unit ER are filled with the most significant bit (MSB) of the first operand OPER
1
in the extended instruction word, and then the position of the same bit as the first operand OPER
1
of the extended instruction word is filled with the first operand OPER
1
in the extended instruction word.
If the following instruction word is an extended instruction word, extended data produced by operating and processing the first operand OPER
1
stored in the extended data storage unit ER is shifted to the upper bit as many as the number of bits of a second operand OPER
2
, and the second operand OPER
2
is placed on the lower bit which is empty in the extended data storage unit ER. Thus, the extended data storage unit ER places the second operand OPER
2
and the first operand OPER
1
from the least significant bit to the upper bit. That is, a value obtained by combining the first operand OPER
1
with the second operand OPER
2
is stored by two extended instruction words in the extended data storage unit ER.
Thus, through the above-described method, the fixed length instruction word system uses an extended instruction word, to thereby produce a constant value larger than the magnitude of the instruction word, or the address of a storage unit.
Since the fixed length instruction word system using the conventional extended instruction word reads an extended instruction word from the storage unit in the same manner as that of a general instruction word, parses the extended instruction word by the command interpreter, and executes the operation of the extended instruction word by an execution unit, the efficiency of both the CPU and the program is lowered.
In view of the above, there exists a need for an extended instruction word folding apparatus which overcomes the above mentioned problems in the prior art. This invention addresses this need in the prior art as well as other needs, which will become apparent to those skilled in the art from this disclosure.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide an extended instruction word folding apparatus for maximizing the efficiency of both a CPU and a program, in which a following extended instruction word is processed during the time of reading and executing a general instruction word in order to use a constant value larger than the magnitude of the general instruction word, or the address of a storage unit, to thereby immediately process a general instruction word subsequent to the following extended instruction word.
To accomplish the above object of the present invention, there is provided an extended instruction word folding apparatus comprises: an instruction word storage unit for storing instruction words including a plurality of general instruction words and extended instruction words; a temporary storage unit including a plurality of buffers for pre-fetching the plurality of instruction words from the instruction word storage unit and storing the pre-fetched instruction words therein; an instruction word search unit for receiving the plurality of instruction words pre-fetched from the instruction word storage unit to the temporary storage unit, decoding the received instruction words, and outputting a position signal representing the position of a general instruction word and the positions of one or more successive extended instruction words, among the instruction words stored in the temporary storage unit; an instruction word selector for selecting a buffer in which a general instruction word is stored among the instruction words stored in each buffer of the temporary storage unit, and outputting the general instruction word sequentially, according to the position signal output from the instruction word search unit; a general instruction word parser for receiving a general instruction word output from the instruction word selector and outputting a plurality of control signals for executing the general instruction word; an extended data parser for performing an operational processing of operands of one or more successive extended instruction words among the instruction words stored in each buffer of the temporary storage unit, according to the position signal output from the instruction word search unit, and outputting extended data; and an extended data storage unit for storing the extended data received from the extended data parser.
Preferably, the instruction word search unit co
Cho Kyung Youn
Kim Hyun Gyu
Lee Geun Taek
Lee Heui
Lim Jong Yoon
Asia Design Co., Ltd.
Cantor & Colburn LLP
Pan Daniel H.
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